scholarly journals Stabilization of negative capacitance in ferroelectric capacitors with and without a metal interlayer

Nanoscale ◽  
2020 ◽  
Vol 12 (10) ◽  
pp. 6121-6129
Author(s):  
T. Rollo ◽  
F. Blanchini ◽  
G. Giordano ◽  
R. Specogna ◽  
D. Esseni
Keyword(s):  
Materials Science ◽  
Electronic Devices ◽  
Ferroelectric Material ◽  
Negative Capacitance ◽  
Science Topic ◽  
Ferroelectric Capacitors

The negative capacitance operation of a ferroelectric material is not only an intriguing materials science topic, but also a property with important technological applications in nanoscale electronic devices.

Negative capacitance in epitaxial ferroelectric capacitors evidenced by dynamic dielectric characterization

2021 ◽  
Vol 26 ◽  
pp. 102076
Author(s):  
Georgia Andra Boni ◽  
Cristina Chirila ◽  
Lucian Dragos Filip ◽  
Ioana Pintilie ◽  
Lucian Pintilie
Keyword(s):  
Negative Capacitance ◽  
Dielectric Characterization ◽  
Ferroelectric Capacitors

Insight into the influence of thermodynamic coefficients on transient negative capacitance in the HZO ferroelectric capacitors

2021 ◽  
Author(s):  
Yuan-Yuan Zhang ◽  
Xiao-Qing Sun ◽  
Jun-Shuai Chai ◽  
Hao Xu ◽  
Xue-Li Ma ◽  
...  
Keyword(s):  
Negative Capacitance ◽  
Ferroelectric Capacitors ◽  
Insight Into

Macroscopic and microscopic picture of negative capacitance operation in ferroelectric capacitors

Nanoscale ◽  
2021 ◽  
Author(s):  
David Esseni ◽  
Riccardo Fontanini
Keyword(s):  
Landau Theory ◽  
Ferroelectric Materials ◽  
Negative Capacitance ◽  
Stabilization Condition ◽  
Microscopic Picture ◽  
Ferroelectric Capacitors

The negative capacitance (NC) operation of ferroelectric materials has been originally proposed based on a homogeneous Landau theory, leading to a simple NC stabilization condition expressed in terms of macroscopic...

scholarly journals Thermodynamic driving force of transient negative capacitance of ferroelectric capacitors

2021 ◽  
Vol 119 (2) ◽  
pp. 022901
Author(s):  
Yuanyuan Zhang ◽  
Xiaoqing Sun ◽  
Junshuai Chai ◽  
Hao Xu ◽  
Xueli Ma ◽  
...  
Keyword(s):  
Driving Force ◽  
Negative Capacitance ◽  
Thermodynamic Driving Force ◽  
Ferroelectric Capacitors

En route toward sustainable organic electronics

2020 ◽  
Vol 7 ◽  
Author(s):  
Alexandra Zvezdin ◽  
Eduardo Di Mauro ◽  
Denis Rho ◽  
Clara Santato ◽  
Mohamed Khalil
Keyword(s):  
End Of Life ◽  
Organic Electronics ◽  
Closed Loop ◽  
Materials Science ◽  
Electronic Devices ◽  
Consumer Electronics ◽  
Electronic Equipment ◽  
Processing Strategy ◽  
Closed Loop Systems ◽  
Systematic Collection

ABSTRACT Consumer electronics have caused an unsustainable amount of waste electrical and electronic equipment (WEEE). Organic electronics, by means of eco-design, represent an opportunity to manufacture compostable electronic devices. Waste electrical and electronic equipment (WEEE), or e-waste, is defined as the waste of any device that uses a power source and that has reached its end of life. Disposing of WEEE at landfill sites has been identified as an inefficient solid waste processing strategy as well as a threat to human health and the environment. In the effort to mitigate the problem, practices such as (i) designing products for durability, reparability, and safe recycling, and (ii) promoting closed-loop systems based on systematic collection and reuse/refurbishment have been identified. In this perspective, we introduce a complementary route to making electronics more sustainable: organic electronics based on biodegradable materials and devices. Biodegradable organic electronics lie at the intersection of research in chemistry, materials science, device engineering, bioelectronics, microbiology, and toxicology. The design of organic electronics for standardized biodegradability will allow composting to be an end-of-life option.

The Fabrication of High-Speed Electronic Devices by Ion-Beam Synthesis of GexSi1-x Strained Layers

1996 ◽  
Vol 438 ◽  
Author(s):  
R. G. Elliman ◽  
H. Jiang ◽  
W. C. Wong ◽  
P. Kringhøj
Keyword(s):  
Oxidation Rate ◽  
Field Effect ◽  
High Speed ◽  
Materials Science ◽  
Field Effect Transistors ◽  
Solid Phase ◽  
Ion Beam ◽  
Electronic Devices ◽  
Solid Phase Epitaxy ◽  
Strained Layers

AbstractGexSi1-x, strained layers can be fabricated by Ge implantation and solid-phase epitaxy and can be used in electronic devices to improve their performance. Several important materials science issues are addressed, including the effect of the strain on solid-phase-epitaxy, the effect of oxidation on the implanted Ge distribution, and the effect of Ge on the oxidation rate of Si. The potential of this process is demonstrated by comparing the performance of metal-oxidesemiconductor field-effect-transistors (MOSFETs) employing ion-beam synthesised GeSi strained layer channel regions with that of Si-only devices.

scholarly journals EFFECT OF FERRO ELECTRIC THICKNESS ON NEGATIVE CAPACITANCE FET (NCFET)

2021 ◽  
Vol 22 (1) ◽  
pp. 339-346
Author(s):  
Muhaimin Bin Mohd Hashim ◽  
AHM Zahirul ALAM ◽  
Naimah Binti Darmis
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Low Voltage ◽  
New Technology ◽  
Ferroelectric Material ◽  
Operating Voltage ◽  
Negative Capacitance ◽  
Channel Potential ◽  
Effect Transistor ◽  
The One

Conventional Field Effect Transistor (FET) are well known to require at least 60mV/decade at 300K change in the channel potential to change the current by a factor of 10. Due to this, 60mV/decade becomes the bottleneck of this day transistor. A comprehensive study of the Negative Capacitance Field Effect Transistor (NCFETis presented.  This paper shows the effect of ferroelectric material in MOSFET structure by replacing the insulator in the conventional MOSFET. It should be possible to obtain a steeper subthreshold swing (SS) compared to the one without a ferroelectric material layer, thus breaking the fundamental limit on the operating voltage of MOSFET.  27% of the subthreshold slope reduction is observed by introducing ferroelectric in the dielectric layer compared to the conventional MOSFETs. Hence, the power dissipation in MOSFET can be mitigated and shine to a new technology of a low voltage/low power transistor operation. ABSTRAK: Transistor Kesan Medan Konvensional (FET) terkenal memerlukan sekurang-kurangnya 60mV / dekad pada 300K perubahan pada saluran yang berpotensi untuk mengubah arus dengan faktor 10. Oleh kerana itu, 60mV / dekad menjadi hambatan transistor hari ini. Kajian komprehensif mengenai Negative Capacitance Field Effect Transistor (NCFETis dikemukakan. Makalah ini menunjukkan kesan bahan ferroelektrik dalam struktur MOSFET dengan mengganti penebat dalam MOSFET konvensional. Sebaiknya dapatkan swing swing subthreshold (SS) yang lebih curam berbanding dengan satu tanpa lapisan bahan ferroelektrik, sehingga melanggar had asas pada voltan operasi MOSFET. 27% pengurangan cerun subthreshold diperhatikan dengan memperkenalkan ferroelektrik di lapisan dielektrik berbanding dengan MOSFET konvensional. Oleh itu, pelesapan daya dalam MOSFET dapat dikurangkan dan bersinar dengan teknologi baru operasi transistor voltan rendah / kuasa rendah.

Optimization of Si-doped HfO2 ferroelectric material-based negative capacitance junctionless TFET: Impact of temperature on RF/linearity performance

2020 ◽  
Vol 34 (27) ◽  
pp. 2050242
Author(s):  
Shradhya Singh ◽  
Sangeeta Singh ◽  
Alok Naugarhiya
Keyword(s):  
Temperature Variation ◽  
Ferroelectric Material ◽  
Asymmetric Structure ◽  
Negative Capacitance ◽  
Performance Parameters ◽  
Device Structure ◽  
Ultra Low Power ◽  
Si Doped ◽  
Rf Performance ◽  
The Impact

This paper addresses the effect of temperature variation on the performance of a novel device structure Si-doped Hf[Formula: see text] negative capacitance junctionless tunnel field effect transistor (Si:Hf[Formula: see text] NC-JLTFET). Here, Si:Hf[Formula: see text] ferroelectric material is deployed as gate stack along with high-K gate dielectric Hf[Formula: see text]. Si:Hf[Formula: see text] ferroelectric material generates NC effect during the device operation. This phenomenon is an effective technique for intrinsic voltage amplification, reduction in power supply, as well as minimization of power dissipation. The proposed device structure has two variants, symmetric and asymmetric with respect to the oxide thickness between electrode and Si body at both drain and source sides. As band-to-band tunneling in TFET is temperature dependent, it is very crucial to analyze the impact of temperature variation on the device performance. This work is mainly focused on investigating the device dc performance parameters, analog/RF performance parameters and linearity performance parameters by observing the impact of temperature variation. The device characteristics reveal that for dc and RF performance parameters, asymmetric structure shows better result. Highest [Formula: see text] ratio and minimum SS are reported as [Formula: see text] and 20.038 mV/dec, respectively, at 300K for asymmetric structure. At elevated temperatures higher cutoff frequency and reduced intrinsic delay project the device as a strong candidate for ultra low-power and high switching speed applications. Further, the reported device shows better linearity performance at higher temperatures.

Sign in / Sign up

Export Citation Format

Share Document