scholarly journals A RET-supported logic gate combinatorial library to enable modeling and implementation of intelligent logic functions

2016 ◽  
Vol 7 (3) ◽  
pp. 1853-1861 ◽  
Author(s):  
Ru-Ru Gao ◽  
Shuo Shi ◽  
Ying Zhu ◽  
Hai-Liang Huang ◽  
Tian-Ming Yao
Keyword(s):  
Combinatorial Library ◽  
Logic Gate ◽  
Logic Gates ◽  
Basic Logic ◽  
Parity Checker ◽  
Nor Gate ◽  
Logic Functions

A logic gate combinatorial library, including basic logic gates, a single three-input NOR gate, and combinatorial gates to realize intelligent logic functions (keypad-lock, parity checker) is constructed.

scholarly journals Analog Low-Voltage Current-Mode Implementation of Digital Logic Gates

2003 ◽  
Vol 26 (2) ◽  
pp. 111-114 ◽  
Author(s):  
Muhammad Taher Abuelma'atti
Keyword(s):  
Power Series ◽  
Low Voltage ◽  
Logic Gates ◽  
Current Mode ◽  
New Technique ◽  
Basic Logic ◽  
Spice Simulation ◽  
Simulation Results ◽  
A New Technique ◽  
Logic Functions

In this letter a new technique is introduced for implementing the basic logic functions using analog current-mode techniques. By expanding the logic functions in power series expressions, and using summers and multipliers, realization of the basic logic functions is simplified. Since no transistors are working in saturation, the problem of fan-out is alleviated. To illustrate the proposed technique, a circuit for simultaneous realization of the logic functions NOT, OR, NAND and XOR is considered. SPICE simulation results, obtained with 3 V supply, are included

Function Expansion of a Chaotic Logic Unit

2010 ◽  
Vol 171-172 ◽  
pp. 283-287
Author(s):  
Yi Yan Sheng ◽  
Wen Bo Liu
Keyword(s):  
Numerical Model ◽  
Circuit Design ◽  
Simulation Analysis ◽  
Circuit Simulation ◽  
Logic Gate ◽  
Logic Gates ◽  
Control Voltage ◽  
Computing Unit ◽  
Nor Gate ◽  
The Impact

Chaos computing is a new circuit design scheme of using chaos computing units to achieve reconfigurable logic gates. The computing unit can function as different kinds of logic gates by changing external parameters. In this paper, the possibilities of expanding the function of a chaotic NOR gate proposed in the literature is studied. The numerical model for the circuit design was built by constructing differential equations fit for Matlab integration mechanism. Besides, numerical model for integrator saturation was built to make results of numerical simulation conform to that of circuit simulation. Analysis of the impact of integrator saturation was done. With the analysis and by changing the control voltage, NAND function was expanded for the original chaotic logic gate that was only able to function as a NOR gate. By adding the function control signal to the input end and setting the voltage of it to different levels, the computing unit becomes a real time reconfigurable one.

scholarly journals Multifunctional Logic Gate by Means of Nanodot Array with Different Arrangements

2013 ◽  
Vol 2013 ◽  
pp. 1-7
Author(s):  
Yasuo Takahashi ◽  
Shinichiro Ueno ◽  
Masashi Arita
Keyword(s):  
Logic Gate ◽  
Logic Gates ◽  
Nanodot Array ◽  
Nanodot Arrays ◽  
Single Electronics ◽  
Positive Sense ◽  
Negative Effect ◽  
Device Applications ◽  
Logic Functions ◽  
Exclusive Or

Multifunctional logic gate devices consisting of a nanodot array are studied from the viewpoint of single electronics. In a nanodot array, the dots come in a random variety of sizes, which sometimes has a negative effect on the performance of electrical device applications. Here, this feature is used in a positive sense to achieve higher functionality in the form of flexible logic gates with low power consumption in which the variability of logic functions is guaranteed. Nanodot arrays with two input gates and one control gate in a variety of arrangements are considered, in which the two-input logic functions (such as NAND, NOR, or exclusive-OR (XOR) gates) are selected by changing the voltage applied to the control gate. To ensure the flexibility of the device, it is important to guarantee the performance with any one of the six important logic functions: NAND, AND, NOR, OR, XOR, and XNOR. We ran a selection simulation using a nanodot array consisting of six nanodots with different dot arrangements to clarify the relation between the variability of the logic functions and the dot arrangements.

scholarly journals A Reconfigurable Logic Cell Based on a Simple Dynamical System

2013 ◽  
Vol 2013 ◽  
pp. 1-7 ◽  
Author(s):  
Lixiang Li ◽  
Chunyu Yang ◽  
Sili Hui ◽  
Wenwen Yu ◽  
Jürgen Kurths ◽  
...  
Keyword(s):  
Dynamical System ◽  
Logic Gate ◽  
Dynamic Logic ◽  
Logic Gates ◽  
Transformation Method ◽  
General Purpose ◽  
Reconfigurable Logic ◽  
Computer Chips ◽  
Threshold Mechanism ◽  
Logic Functions

This paper introduces a new scheme to achieve a dynamic logic gate which can be adjusted flexibly to obtain different logic functions by adjusting specific parameters of a dynamical system. Based on graphical tools and the threshold mechanism, the distribution of different logic gates is studied, and a transformation method between different logics is given. Analyzing the performance of the dynamical system in the presence of noise, we discover that it is resistant to system noise. Moreover, we find some part of the system can be considered as a leaky integrator which has been already widely applied in engineering. Finally, we provide a proof-of-principle hardware implementation of the proposed scheme to illustrate its effectiveness. With the proposed scheme in hand, it is convenient to build the flexible, robust, and general purpose computing devices such as various network coding routers, communication encoders or decoders, and reconfigurable computer chips.

scholarly journals Dynamic power dissipation of basic logic gates

2021 ◽  
Author(s):  
Katayoun Pourbahri
Keyword(s):  
Power Dissipation ◽  
Logic Gate ◽  
Load Condition ◽  
Order Relation ◽  
Logic Gates ◽  
Cmos Technology ◽  
Output Coupling ◽  
Basic Logic ◽  
Dynamic Power ◽  
Proposed Model

In this thesis, a model is proposed to estimate the dynamic power dissipation of CMOS logic gate that is loaded with identical logic gates. The proposed model is based on parsitic capacitance, input capacitance and input-to-output coupling capacitance of the gate. Also, model takes into account transistor width and has a second order relation with fanout. Using 0.13um CMOS technology and netlist (Cadence), basic logic gates are designed and loaded by identical basic logic gates. Basic logic gates dynamic power are simulated and compared with the calculated values of proposed model over a range of transistor sizes and capacitive load condition. The proposed model shows a good agreement with the simulated value of dynamic power dissipation of basic logic gates that are loaded by identical basic logic gates.

scholarly journals SiAlS (Simple Alarm System) Based Light Dependent Resistor (LDR) and Basic Logic Gate as an Attempt to Preventing on Helmet Theft

2019 ◽  
Vol 2 ◽  
pp. 229-230
Author(s):  
Aji Rahmadi ◽  
Adi Ahmad Dimisa ◽  
Asep Kurniawan ◽  
Frida Agung Rakhmadi
Keyword(s):  
Success Rate ◽  
Logic Gate ◽  
Logic Gates ◽  
Alarm System ◽  
Basic Logic ◽  
Alarm Systems ◽  
Working Principle ◽  
Three Stages ◽  
Rearview Mirror

Research on the Light Dependent Resistor (LDR) and the basic logic gates in the designing and manufacturing SiAlS (Simple Alarm System) as an attempt to Prevent theft helmet on had been done. This research was conducted aiming to create and Characterize alarm system. This study was intended to Prevent theft of the helmet. The method used in this research is divided into three stages, designing, manufacturing and testing. The working principle of this alarm system is when the helmet is mounted in the rearview mirror, the LDR will be closed so that the resistance increases the which causes the alarm to Become inactive. However, if the helmet is taken, the alarm will activate because The resistance decreases. However, the alarm will not work if the sensor cable is cut by the thief. To Overcome this problem, additional circuits are made using a NOT logic gates. The results of this research are prototypes in testing alarm systems and alarm systems get a 100% success rate. The advantage of this alarm systems are cheap and simple, Because it does not use a microcontroller and can be made individually.

scholarly journals Contextual dependencies expand the re-usability of genetic inverters

2020 ◽  
Author(s):  
Huseyin Tas ◽  
Lewis Grozinger ◽  
Ruud Stoof ◽  
Victor de Lorenzo ◽  
Angel Goñi-Moreno
Keyword(s):  
Synthetic Biology ◽  
Computational Analysis ◽  
Logic Gate ◽  
Logic Gates ◽  
Boolean Logic ◽  
Regulatory Proteins ◽  
Genetic Circuits ◽  
Genetic Construct ◽  
Genetic Components ◽  
Logic Functions

The design and implementation of Boolean logic functions in living cells has become a very active field within synthetic biology. By controlling networks of regulatory proteins, novel genetic circuits are engineered to generate predefined output responses. Although many current implementations focus solely on the genetic components of the circuit, the host context in which the circuit performs is crucial for its outcome. Here, we characterise 20 genetic NOT logic gates (inverters) in up to 7 bacterial-based contexts each, to finally generate 135 different functions. The contexts we focus on are particular combinations of four plasmid backbones and three hosts, two Escherichia coli and one Pseudomonas putida strains. Each NOT logic gate shows seven different logic behaviours, depending on the context. That is, gates can be reconfigured to fit response requirements by changing only contextual parameters. Computational analysis shows that this range of behaviours improves the compatibility between gates, because there are considerably more possibilities for combination than when considering a unique function per genetic construct. Finally, we address the issue of interoperability and portability by measuring, scoring, and comparing gate performance across contexts. Rather than being a limitation, we argue that the effect of the genetic background on synthetic constructs expand the scope of the functions that can be engineered in complex cellular environments, and advocate for considering context as a fundamental design parameter for synthetic biology.

Low-Voltage Low-Power CMOS-Based Current-Mode Implementation of Digital Logic Gates and Combinational Circuits

2021 ◽  
pp. 2150212
Author(s):  
Prabhat Gupta ◽  
Raina Banerjee ◽  
Ravish Sharma
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Geometric Mean ◽  
Series Representation ◽  
Logic Gates ◽  
Current Mode ◽  
Combinational Circuits ◽  
Basic Logic ◽  
Power Circuit ◽  
Logic Functions

In this paper, a new low-voltage low-power circuit is introduced for implementing CMOS-based basic logic functions using the analog current-mode techniques. The logic functions have been realized by using their expansion in Power Series representation, a Squaring circuit and a Geometric Mean circuit. To illustrate the proposed method, simultaneous realization of the basic logic functions NOT, OR, AND, XOR, NOR, NAND and XNOR in a single circuit is considered. Furthermore, these functions have been used to realize various combinational circuits including full-adder, full-subtractor, etc. SPICE simulation results, obtained with 1.5-V supply, are included.

scholarly journals Dynamic power dissipation of basic logic gates

2021 ◽  
Author(s):  
Katayoun Pourbahri
Keyword(s):  
Power Dissipation ◽  
Logic Gate ◽  
Load Condition ◽  
Order Relation ◽  
Logic Gates ◽  
Cmos Technology ◽  
Output Coupling ◽  
Basic Logic ◽  
Dynamic Power ◽  
Proposed Model

In this thesis, a model is proposed to estimate the dynamic power dissipation of CMOS logic gate that is loaded with identical logic gates. The proposed model is based on parsitic capacitance, input capacitance and input-to-output coupling capacitance of the gate. Also, model takes into account transistor width and has a second order relation with fanout. Using 0.13um CMOS technology and netlist (Cadence), basic logic gates are designed and loaded by identical basic logic gates. Basic logic gates dynamic power are simulated and compared with the calculated values of proposed model over a range of transistor sizes and capacitive load condition. The proposed model shows a good agreement with the simulated value of dynamic power dissipation of basic logic gates that are loaded by identical basic logic gates.

Design of Universal Logic Gates Using Homo and Hetero-Junction Double Gate TFETs with Pseudo-Derived Logic

2021 ◽  
Author(s):  
Lokesh B ◽  
Sai Pavan kumar K ◽  
Pown M ◽  
Lakshmi B
Keyword(s):  
Power Consumption ◽  
Logic Gate ◽  
Logic Gates ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Nand Gate ◽  
Double Gate ◽  
Nor Gate ◽  
Nor Logic Gate

Abstract This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 103 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 103 times and less propagation delay than that of hetero-junction NOR logic circuit

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