An empirical study-based state space model for multilayer overlay errors in the step-scan lithography process
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In semiconductor manufacturing, the multilayer overlay lithography process is a typical multistage manufacturing process; one of the key factors that restrict the reliability and yield of integrated circuit chips is overlay error between the layers.
2012 ◽
Vol 217-219
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pp. 2580-2584
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2019 ◽
Vol 1168
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pp. 052008
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2002 ◽
Vol 124
(2)
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pp. 313-322
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Keyword(s):
Development of L1-norm sliding mode observer for sensor fault diagnosis of an industrial gas turbine
2021 ◽
pp. 095965182199617
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