Low voltage and high ON/OFF ratio field-effect transistors based on CVD MoS2 and ultra high-k gate dielectric PZT

Nanoscale ◽  
2015 ◽  
Vol 7 (19) ◽  
pp. 8695-8700 ◽  
Author(s):  
Changjian Zhou ◽  
Xinsheng Wang ◽  
Salahuddin Raju ◽  
Ziyuan Lin ◽  
Daniel Villaroman ◽  
...  
Keyword(s):  
Low Power ◽  
Field Effect ◽  
Gate Dielectric ◽  
Low Voltage ◽  
Field Effect Transistors ◽  
Power Device ◽  
Enhancement Mode ◽  
High K ◽  
High K Gate Dielectric

Ultra high-k dielectric enables low-voltage enhancement-mode MoS2 transistor with high ON/OFF ratio, leading to low-power device.

On the 1/f noise of triple-gate field-effect transistors with high-k gate dielectric

2009 ◽  
Vol 95 (3) ◽  
pp. 032101 ◽  
Author(s):  
N. Lukyanchikova ◽  
N. Garbar ◽  
V Kudina ◽  
A. Smolanka ◽  
S. Put ◽  
...  
Keyword(s):  
Field Effect ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
High K ◽  
High K Gate Dielectric

Trap evaluations of metal/oxide/silicon field-effect transistors with high-k gate dielectric using charge pumping method

2002 ◽  
Vol 81 (11) ◽  
pp. 2050-2052 ◽  
Author(s):  
Ga-Won Lee ◽  
Jae-Hee Lee ◽  
Hae-Wang Lee ◽  
Myoung-Kyu Park ◽  
Dae-Gwan Kang ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Charge Pumping ◽  
High K ◽  
Metal Oxide Silicon ◽  
High K Gate Dielectric

Performance Evaluation of InGaAs Dielectric Engineered Tunnel Field-Effect Transistors

2019 ◽  
Vol 59 ◽  
pp. 149-160
Author(s):  
Sayed Mohammad Tariful Azam ◽  
A.S.M. Bakibillah ◽  
M.A.S. Kamal
Keyword(s):  
Low Power ◽  
Field Effect ◽  
Gate Dielectric ◽  
Field Effect Transistors ◽  
Oxide Thickness ◽  
Potential Candidate ◽  
High K ◽  
Low Power Dissipation ◽  
High Transconductance ◽  
P Type

In this paper for the first time, the performance of Dielectric Engineered Tunnel Field Effect Transistors (DE-TFETs) is evaluated on the InGaAs channel. Two DE-TFETs based on gate-dielectric structures, namely, Device-A and Device-B are modeled and characterized for both n-type and p-type operations to attain low subthreshold slope (SS) and drain induced barrier lowering (DIBL) using La2O3 as high-k gate dielectric. A structural modification of Device-B is illustrated that improves the on-state current (Ion), SS, and DIBL. Then, performance of both devices are analyzed based on physical oxide thickness (Tox). The simulation results show that the modified Device-B has the lowest SS of 15.31 mV/dec and 54.64 mV/dec, Ion/Ioff ratio of ~109 and ~106 with off-state current (Ioff) of ~10-15 A/µm and ~10-12 A/µm for n-DE-TFET and p-DE-TFET, respectively. Furthermore, the performance parameters of both devices are studied for digital and analog applications and it is found that the modified Device-B can be a potential candidate for future digital applications due to its low power dissipation of 13.55 µW/µm and 27.56 µW/µm for n-DE-TFET and p-DE-TFET, respectively. On the other hand, Device-A shows high transconductance (gm) of 722.52 µS/µm and 424.3 µS/µm and cut-off frequency (fT) of 211.95 GHz and 290.86 GHz for n-DE-TFET and p-DE-TFET, respectively, and can be a viable candidate for future low power analog applications.

Sign in / Sign up

Export Citation Format

Share Document