Polystyrene-block-poly(methylmethacrylate) composite material film as a gate dielectric for plastic thin-film transistor applications

RSC Advances ◽  
2014 ◽  
Vol 4 (36) ◽  
pp. 18493-18502 ◽  
Author(s):  
Jagan Singh Meena ◽  
Min-Ching Chu ◽  
Ranjodh Singh ◽  
Chung-Shu Wu ◽  
Umesh Chand ◽  
...  
Keyword(s):  
Thin Film ◽  
Dielectric Constant ◽  
Gate Dielectric ◽  
High Surface ◽  
Thin Film Transistor ◽  
Plastic Substrate ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High Surface Energy ◽  
Low Temperature Process

Low-temperature process PS-b-PMMA composite film as gate dielectric deposited over plastic substrate, which exhibits high surface energy, high air stability, very low leakage current and better dielectric constant compared to their conventional polymer dielectrics for use in ZnO–TFT applications.

High k PVP titanium dioxide composite dielectric with low leakage current for thin film transistor

2021 ◽  
pp. 106413
Author(s):  
Yuexin Yang ◽  
Zhuohui Xu ◽  
Tian Qiu ◽  
Honglong Ning ◽  
Jinyao Zhong ◽  
...  
Keyword(s):  
Thin Film ◽  
Titanium Dioxide ◽  
Leakage Current ◽  
Thin Film Transistor ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K

Hot-wire CVD a-Si:H TFT on Plastic Substrates

2006 ◽  
Vol 910 ◽  
Author(s):  
Farhad Taghibakhsh ◽  
K.S. Karim
Keyword(s):  
Thin Film ◽  
Chemical Vapor Deposition ◽  
Amorphous Silicon ◽  
Vapor Deposition ◽  
Thin Film Transistors ◽  
Gate Dielectric ◽  
Chemical Vapor ◽  
Plastic Substrate ◽  
Hot Wire ◽  
Low Leakage

AbstractFabrication of hot-wire chemical vapor deposition (HWCVD) of amorphous silicon (a-Si) thin film transistors (TFT) on thin polyamide sheets is reported. A single graphite filament at 1500 °C was used for HWCVD and device quality amorphous silicon films were deposited with no thermal damage to plastic substrate. Top-gate staggered thin film transistors (TFTs) were fabricated at 150°C using hot-wire deposited a-Si channel, Plasma enhanced chemical vapor deposition (PECVD) silicon nitride gate dielectric, and microcrystalline n+ drain/source contacts. Low leakage current of 5×10-13 A, high switching current ratio of 1.3×107, and small sub threshold swing of 0.3 V/dec was obtained for TFTs with aspect ratio of 1300μm/100μm. The field effect mobility was extracted to be 0.34 cm2/V.s.

Bio Organic-Based Gate Dielectric Materials for Thin Film Transistors

2012 ◽  
Vol 1467 ◽  
Author(s):  
James G. Grote ◽  
Fahima Ouchen ◽  
Donna M. Joyce ◽  
Kristi M. Singh ◽  
Narayanan Venkat ◽  
...  
Keyword(s):  
Thin Film ◽  
Dielectric Constant ◽  
Gate Dielectric ◽  
Variable Temperature ◽  
Thin Film Transistor ◽  
Dielectric Materials ◽  
Large Temperature ◽  
Hybrid Films ◽  
Dielectric Characterization ◽  
High Dielectric

ABSTRACTThe potential of bio-dielectrics for thin film transistor applications was explored via the incorporation of titanium dioxide (TiO2) nanoparticles, rutile form, a high dielectric constant (ε) ceramic, in the deoxyribonucleic acid (DNA) bio-polymer. The DNA-ceramic hybrid films were fabricated from stable suspensions of the TiO2 nanoparticles in viscous, aqueous DNA solutions. Dielectric characterization revealed that the incorporation of TiO2 in DNA resulted in enhanced dielectric constant (14.3 at 1 kHz for 40 wt % TiO2) relative to that of DNA in the entire frequency range of 1 kHz-1 MHz. Variable temperature dielectric measurements, in the 20-80°C range, of the DNA-TiO2 films revealed that the ceramic additive stabilizes DNA against large temperature dependent variations in both ε and the dielectric loss factor tan δ. The bulk resistivity of the DNA-TiO2 hybrid films was measured to be two to three orders of magnitude higher than that of the control DNA films, indicating their potential for utilization as insulating dielectrics in transistor and capacitor applications.

scholarly journals Hybrid La2O3-cPVP Dielectric for Organic Thin Film Transistor Applications

2022 ◽  
Author(s):  
SAGARIKA KHOUND ◽  
Jayanta Kumar Sarmah ◽  
RANJIT SARMA
Keyword(s):  
Thin Film ◽  
Organic Semiconductors ◽  
Gate Dielectrics ◽  
Thin Film Transistor ◽  
Single Layer ◽  
Rare Earth Oxide ◽  
Electrical Performance ◽  
Organic Thin Film ◽  
Low Leakage ◽  
Low Leakage Current

Abstract In this work, we have studied the electrical performance of cross-linked polyvinyl phenol (cPVP) modified lanthanum oxide (La2O3) bilayer dielectric film in pentacene thin film transistors (TFT). A simple spin-coating and room temperature operated cross-linking reaction of the hydroxyl moieties of PVP and the nitrogen groups of PMF were carried out to form the cross-linked PVP. The deposition of a thin 30 nm cPVP layer over the La2O3 layer provided a low leakage current (<10−7A/cm2), causing a reduction in the interface trap density. Besides, the modified surface properties of the La2O3 layer were favorable for the growth of pentacene organic semiconductors. As a result, the current on-off ratio and the sub-threshold slope was improved from 104 and 1.0 V/decade to 105 and 0.67 V/decade. The La2O3∕cPVP pentacene TFT operated at −10 V also exhibited improvement in the field-effect mobility to 0.71 cm2/Vs from 0.48 cm2/Vs for the single-layer La2O3 (130 nm) device. Thus, our work demonstrates that the rare earth oxide La2O3 with cPVP is an excellent dielectric system in the context of emerging transistors with hybrid polymer gate dielectrics.

Low Leakage Current Patterned Polymeric Transistors with PAG Assisted Cross-linking PVP as Gate Dielectric and Passivation Layers

2008 ◽  
Vol 1091 ◽  
Author(s):  
Cheng-Chin Liu ◽  
Kuo-Jui Chang ◽  
Feng-Yu Yang ◽  
Ta-Chuan Liao ◽  
Huang-Chung Cheng
Keyword(s):  
Low Temperature ◽  
Leakage Current ◽  
Gate Dielectric ◽  
Gate Dielectrics ◽  
Thin Film Transistor ◽  
Subthreshold Swing ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Passivation Layers ◽  
Amorphous Si

AbstractWe have successfully proposed a patterned P3HT thin-film transistor with cross-linked PVP as a passivation material which was cured at low temperature. The active P3HT layer was isolated via photolithographic technique and O2 plasma RIE etching process. In this method, the leakage current could be reduced effectively compared with that of non-patterned device. Although the mobility was degraded 40 %, but the on/off ratio was significantly improved by over three orders and also the subthreshold swing was compatible with the amorphous Si-TFTs (∼1.5 V/decade). Moreover, we also employed this low temperature curing PVP (120 0C) films as the gate dielectrics which exhibited excellent insulating property with high on/off ratio 1.58×104 and good subthreshold swing 1.66 V/decade.

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