Access Time to the Internal Lexicon: Bilingual and Monolingual Subjects

1973 ◽  
Author(s):  
Roy Lachman ◽  
Janet L. Mistler-lachman ◽  
J. R. Holloway
Keyword(s):  
Access Time ◽  
Internal Lexicon

Web Service Implementation in Logistics Company uses JSON Web Token and RC4 Cryptography Algorithm

2020 ◽  
Vol 4 (3) ◽  
pp. 591-600
Author(s):  
Mochammad Rizky Royani ◽  
Arief Wibowo
Keyword(s):  
Web Service ◽  
Data Storage ◽  
Growth Potential ◽  
Easy Access ◽  
Access Time ◽  
Mobile Platforms ◽  
Logistics Service ◽  
Authentication Mechanism ◽  
Cryptographic Algorithm ◽  
Service Application

The development of e-commerce in Indonesia in the last five years has significantly increased the growth for logistics service companies. The Indonesian Logistics and Forwarders Association (ALFI) has predicted the growth potential of the logistics business in Indonesia to reach more than 30% by 2020. One of the efforts of logistics business companies to improve services in the logistics services business competition is to implement web service technology on mobile platforms, to easy access to services for customers. This research aims to build a web service with a RESTful approach. The REST architecture has limitations in the form of no authentication mechanism, so users can access and modify data. To improve its services, JSON Web Token (JWT) technology is needed in the authentication process and security of access rights. In terms of data storage and transmission security, a cryptographic algorithm is also needed to encrypt and maintain confidentiality in the database. RC4 algorithm is a cryptographic algorithm that is famous for its speed in the encoding process. RC4 encryption results are processed with the Base64 Algorithm so that encrypted messages can be stored in a database. The combination of the RC4 method with the Base64 method has strengthened aspects of database security. This research resulted in a prototype application that was built with a combination of web service methods, JWT and cryptographic techniques. The test results show that the web service application at the logistics service company that was created can run well with relatively fast access time, which is an average of 176 ms. With this access time, the process of managing data and information becomes more efficient because before making this application the process of handling a transaction takes up to 20 minutes.

Comparison Between Supraclavicular and Infraclavicular Approach in Subclavian Vein Catheterization in Tertiary Center of Nepal

2020 ◽  
Vol 3 (2) ◽  
pp. 111-115
Author(s):  
Robin Khapung ◽  
Jeju Nath Pokharel ◽  
Kiran Kumar KC ◽  
Kripa Pradhan ◽  
Uma Gurung ◽  
...  
Keyword(s):  
Success Rate ◽  
Subclavian Vein ◽  
Guide Wire ◽  
Femoral Vein ◽  
Access Time ◽  
P Value ◽  
Central Vein ◽  
Chi Square ◽  
Tertiary Center ◽  
Vein Catheterization

Introduction: Central vein catheterization can be introduced in subclavian vein (SCV), internal jugular vein or femoral vein for volume resuscitation and invasive monitoring technique. Due to anatomical advantage and lesser risk of infection subclavian vein is preferred. Either supraclavicular (SC) or infraclavicular (IC) approach could be used for subclavian vein catheterization. The aim of the study was to compare SC and IC approach in ease of catheterization of SCV and record the complications present if any. Methods and materials: This was a hospital based comparative, interventional study conducted from November 2016 to October 2017 in Operation Theater in Bir Hospital. In this study, 70 patients for elective surgical cases meeting the inclusion criteria were randomly enrolled. Then samples were equally divided by lottery into either supraclavicular or infraclavicular approach groups. The Access time, cannulation success rate, attempts made for successful cannulation of vein, easy insertion of catheter and guide wire, approximate inserted length of catheter and associated complications in both groups were recorded. Data was entered in statistical software SPSS 16. Chi-square test was used. P value < 0.05 was considered significant. Results: The mean access time in group SC for SCV catheterization was 2.12 ± 0.81 min compared to 2.83 ± 0.99 min in group IC (p-value= 0.002). The overall success rate in catheterization of the right SCV using SC approach (34 / 35) was better as compared with group IC (33 / 35) using IC approach. First successful attempt in the SC group was 74.28% as compared with 57.14% in the IC group. Conclusion: The SC approach of SCV catheterization can be considered alternative to IC approach in terms of landmark accessibility, success rate and rate of complications.

scholarly journals Decreasing the Miss Rate and Eliminating the Performance Penalty of a Data Filter Cache

2021 ◽  
Vol 18 (3) ◽  
pp. 1-22
Author(s):  
Michael Stokes ◽  
David Whalley ◽  
Soner Onder
Keyword(s):  
Energy Efficient ◽  
Data Access ◽  
Performance Degradation ◽  
Access Time ◽  
Data Cache ◽  
Energy Usage ◽  
Single Cycle ◽  
Performance Penalty

While data filter caches (DFCs) have been shown to be effective at reducing data access energy, they have not been adopted in processors due to the associated performance penalty caused by high DFC miss rates. In this article, we present a design that both decreases the DFC miss rate and completely eliminates the DFC performance penalty even for a level-one data cache (L1 DC) with a single cycle access time. First, we show that a DFC that lazily fills each word in a DFC line from an L1 DC only when the word is referenced is more energy-efficient than eagerly filling the entire DFC line. For a 512B DFC, we are able to eliminate loads of words into the DFC that are never referenced before being evicted, which occurred for about 75% of the words in 32B lines. Second, we demonstrate that a lazily word filled DFC line can effectively share and pack data words from multiple L1 DC lines to lower the DFC miss rate. For a 512B DFC, we completely avoid accessing the L1 DC for loads about 23% of the time and avoid a fully associative L1 DC access for loads 50% of the time, where the DFC only requires about 2.5% of the size of the L1 DC. Finally, we present a method that completely eliminates the DFC performance penalty by speculatively performing DFC tag checks early and only accessing DFC data when a hit is guaranteed. For a 512B DFC, we improve data access energy usage for the DTLB and L1 DC by 33% with no performance degradation.

scholarly journals Pre-Emphasis Pulse Design for Random-Access Memory

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1454
Author(s):  
Yoshihiro Sugiura ◽  
Toru Tanzawa
Keyword(s):  
Time Constant ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Memory Access ◽  
Access Time ◽  
Access Memory ◽  
Delay Times ◽  
Cell Current ◽  
The Impact

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.

scholarly journals Decision Tree-Based Adaptive Reconfigurable Cache Scheme

Algorithms ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 176
Author(s):  
Wei Zhu ◽  
Xiaoyang Zeng
Keyword(s):  
Decision Tree ◽  
Adaptive Algorithms ◽  
Memory Access ◽  
Access Time ◽  
Decision Tree Algorithm ◽  
Verilog Hdl ◽  
Tree Model ◽  
Cache Associativity ◽  
Cache Scheme ◽  
Reconfigurable Cache

Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache coherent protocol. By monitoring the application running state, the cache associativity is periodically tuned to the optimal cache associativity, which is determined by the decision tree model. This paper implements the proposed decision tree-based adaptive reconfigurable cache in the GEM5 simulator and designs the key modules using Verilog HDL. The simulation results show that the proposed decision tree-based adaptive reconfigurable cache reduces the average memory access time compared with other adaptive algorithms.

scholarly journals State Management for Cloud-Native Applications

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 423
Author(s):  
Márk Szalay ◽  
Péter Mátray ◽  
László Toka
Keyword(s):  
Large Scale ◽  
Distributed Databases ◽  
Access Time ◽  
Replica Placement ◽  
State Management ◽  
Placement Decisions ◽  
Dynamic Replication ◽  
Cloud Databases ◽  
Placement Algorithm ◽  
The One

The stateless cloud-native design improves the elasticity and reliability of applications running in the cloud. The design decouples the life-cycle of application states from that of application instances; states are written to and read from cloud databases, and deployed close to the application code to ensure low latency bounds on state access. However, the scalability of applications brings the well-known limitations of distributed databases, in which the states are stored. In this paper, we propose a full-fledged state layer that supports the stateless cloud application design. In order to minimize the inter-host communication due to state externalization, we propose, on the one hand, a system design jointly with a data placement algorithm that places functions’ states across the hosts of a data center. On the other hand, we design a dynamic replication module that decides the proper number of copies for each state to ensure a sweet spot in short state-access time and low network traffic. We evaluate the proposed methods across realistic scenarios. We show that our solution yields state-access delays close to the optimal, and ensures fast replica placement decisions in large-scale settings.

scholarly journals Speeding Up the Write Operation for Multi-Level Cell Phase Change Memory with Programmable Ramp-Down Current Pulses

Micromachines ◽  
2019 ◽  
Vol 10 (7) ◽  
pp. 461 ◽  
Author(s):  
Chenchen Xie ◽  
Xi Li ◽  
Houpeng Chen ◽  
Yang Li ◽  
Yuanguang Liu ◽  
...  
Keyword(s):  
Phase Change ◽  
Current Source ◽  
Phase Change Memory ◽  
Operation Time ◽  
Access Time ◽  
Fully Differential ◽  
Current Pulses ◽  
Multi Level ◽  
The Impact ◽  
Change Memory

Multi-level cell (MLC) phase change memory (PCM) can not only effectively multiply the memory capacity while maintaining the cell area, but also has infinite potential in the application of the artificial neural network. The write and verify scheme is usually adopted to reduce the impact of device-to-device variability at the expense of a greater operation time and more power consumption. This paper proposes a novel write operation for multi-level cell phase change memory: Programmable ramp-down current pulses are utilized to program the RESET initialized memory cells to the expected resistance levels. In addition, a fully differential read circuit with an optional reference current source is employed to complete the readout operation. Eventually, a 2-bit/cell phase change memory chip is presented with a more efficient write operation of a single current pulse and a read access time of 65 ns. Some experiments are implemented to demonstrate the resistance distribution and the drift.

scholarly journals The Route for Ultra-High Recording Density Using Probe-Based Data Storage Device

NANO ◽  
2015 ◽  
Vol 10 (08) ◽  
pp. 1550118 ◽  
Author(s):  
Lei Wang ◽  
Jing Wen ◽  
CiHui Yang ◽  
Shan Gai ◽  
YuanXiu Peng
Keyword(s):  
Phase Change ◽  
Data Storage ◽  
Electrical Contact ◽  
Crystal Nucleation ◽  
Access Time ◽  
Storage Device ◽  
Electrical Contact Resistance ◽  
Low Energy Consumption ◽  
Modeling Techniques ◽  
Second Period

Phase-change probe memory using Ge2Sb2Te5 has been considered as one of the promising candidates as next-generation data storage device due to its ultra-high density, low energy consumption, short access time and long retention time. In order to utmostly mimic the practical setup, and thus fully explore the potential of phase-change probe memory for 10 Tbit/in2 target, some advanced modeling techniques that include threshold-switching, electrical contact resistance, thermal boundary resistance and crystal nucleation-growth, are introduced into the already-established electrothermal model to simulate the write and read performance of phase-change probe memory using an optimal media stack design. The resulting predictions clearly demonstrate the capability of phase-change probe memory to record 10 Tbit/in2 density under pico Joule energy within micro second period.

Sign in / Sign up

Export Citation Format

Share Document