Do the Fillers Uh and Um Signal Delay in Spoken Discourse?

2004 ◽  
Author(s):  
Daniel C. O'Connell ◽  
Sabine Kowal
Keyword(s):  
Signal Delay ◽  
Spoken Discourse

Modeling Spoken Discourse Comprehension Across the Adult Life Span

2008 ◽  
Author(s):  
Sandra Hale ◽  
Mitchell S. Sommers ◽  
Joel Myerson ◽  
Nancy Tye-Murray ◽  
Nathan Rose ◽  
...  
Keyword(s):  
Life Span ◽  
Adult Life ◽  
Discourse Comprehension ◽  
Adult Life Span ◽  
Spoken Discourse

scholarly journals Severe violations of independence in response inhibition tasks

2021 ◽  
Vol 7 (12) ◽  
pp. eabf4355
Author(s):  
Patrick G. Bissett ◽  
Henry M. Jones ◽  
Russell A. Poldrack ◽  
Gordon D. Logan
Keyword(s):  
Response Inhibition ◽  
Theoretical Foundation ◽  
Reaction Times ◽  
Stop Signal ◽  
Experimental Paradigm ◽  
Signal Delay ◽  
Independence Assumption ◽  
Analysis Techniques ◽  
Wide Range ◽  
Saccadic Responses

The stop-signal paradigm, a primary experimental paradigm for understanding cognitive control and response inhibition, rests upon the theoretical foundation of race models, which assume that a go process races independently against a stop process that occurs after a stop-signal delay (SSD). We show that severe violations of this independence assumption at short SSDs occur systematically across a wide range of conditions, including fast and slow reaction times, auditory and visual stop signals, manual and saccadic responses, and especially in selective stopping. We also reanalyze existing data and show that conclusions can change when short SSDs are excluded. Last, we suggest experimental and analysis techniques to address this violation, and propose adjustments to extant models to accommodate this finding.

TDC Implementation Based on Internal Delay Module of FPGA

2013 ◽  
Vol 816-817 ◽  
pp. 1063-1068
Author(s):  
Rou Gang Zhou ◽  
Yun Fei Zhou ◽  
Guang Dou Liu ◽  
Xiao Tu
Keyword(s):  
Nuclear Physics ◽  
Measurement Accuracy ◽  
Laser Interferometer ◽  
Interpolation Method ◽  
Time Measurement ◽  
Clock Signal ◽  
Signal Delay ◽  
Digital Conversion ◽  
Sampling Points ◽  
Stable Performance

Currently the time to digital converter (TDC) integrated in FPGA performs time-to-digital conversion in the carry chain mode and inter-slot offset is caused to be severe by internal wiring in the FPGA. Based on the carry chain interpolation method, this paper proposes the method for using a delay module in FPGA to achieve accurate signal delay. By calculating the phase difference of multi-clock signal between two latch sampling points, the interval between two sampling points was obtained. Experimental results indicate a measurement accuracy of 78ps or 52ps can be reached by precisely collecting time through the delay module in FPGA. Compared to the carry chain interpolation method, this method is significantly advantageous in small inter-slot offset, stable performance and convenient design and can meet the requirement for time measurement or requirement by laser interferometer with a nm-level accuracy in nuclear physics.

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