Control of Gold Surface Diffusion on Si Nanowires

Nano Letters ◽  
2008 ◽  
Vol 8 (5) ◽  
pp. 1544-1550 ◽  
Author(s):  
Martien I. den Hertog ◽  
Jean-Luc Rouviere ◽  
Florian Dhalluin ◽  
Pierre J. Desré ◽  
Pascal Gentile ◽  
...  
Keyword(s):  
Surface Diffusion ◽  
Gold Surface ◽  
Si Nanowires

Control of gold surface diffusion on Si nanowires

2008 ◽  
pp. 125-126
Author(s):  
Martien I. den Hertog ◽  
Jean-Luc. Rouviere ◽  
Florian Dhalluin ◽  
Pierre J. Desré ◽  
Pascal Gentile ◽  
...  
Keyword(s):  
Surface Diffusion ◽  
Gold Surface ◽  
Si Nanowires

Tunneling microscopy, lithography, and surface diffusion on an easily prepared, atomically flat gold surface

1988 ◽  
Vol 63 (3) ◽  
pp. 717-721 ◽  
Author(s):  
J. Schneir ◽  
R. Sonnenfeld ◽  
O. Marti ◽  
P. K. Hansma ◽  
J. E. Demuth ◽  
...  
Keyword(s):  
Surface Diffusion ◽  
Gold Surface ◽  
Tunneling Microscopy ◽  
Atomically Flat

Diffusion in SixGe1−x/Si Nanowire Heterostructures

2007 ◽  
Vol 7 (2) ◽  
pp. 717-720 ◽  
Author(s):  
Xi Zhang ◽  
Joseph Kulik ◽  
Elizabeth C. Dickey
Keyword(s):  
Activation Energy ◽  
Surface Diffusion ◽  
Diffusion Coefficients ◽  
Energy Barrier ◽  
Laser Vaporization ◽  
Si Nanowires ◽  
Activation Energy Barrier ◽  
Nanowire Heterostructures ◽  
Composition Profiles ◽  
Post Synthesis

Si0.48Ge0.52/Si tip/nanowire heterostructures were grown by pulsed laser vaporization (PLV) at a growth temperature of 1100 °C. Ge diffusion in [111]-growth Si nanowires was studied for different post-synthesis annealing temperatures from 200 °C to 800 °C. Ge composition profiles were quantified by energy-dispersive X-ray spectroscopy in a transmission electron microscope. The compositional profiles were modeled by a limited-source diffusion model to extract temperature-dependent diffusion coefficients. The Ge diffusion coefficients followed an Arrhenius relationship with an activation energy of 0.622 ± 0.050 eV. This rather low activation energy barrier is similar to the previously reported activation energy barrier of 0.67 eV for Ge surface diffusion on Si, suggesting that surface diffusion may dominate in nanowires at this length scale.

A theory of contamination in electron microscopes by surface diffusion

1978 ◽  
Vol 36 (1) ◽  
pp. 116-117
Author(s):  
J.T. Fourie
Keyword(s):  
Electron Beam ◽  
Surface Diffusion ◽  
High Vacuum ◽  
Ultra High Vacuum ◽  
Physical Parameters ◽  
Carbon Compounds ◽  
Hydrocarbon Molecules ◽  
Electron Microscopes ◽  
Primary Electrons ◽  
Long Chain

Contamination in electron microscopes can be a serious problem in STEM or in situations where a number of high resolution micrographs are required of the same area in TEM. In modern instruments the environment around the specimen can be made free of the hydrocarbon molecules, which are responsible for contamination, by means of either ultra-high vacuum or cryo-pumping techniques. However, these techniques are not effective against hydrocarbon molecules adsorbed on the specimen surface before or during its introduction into the microscope. The present paper is concerned with a theory of how certain physical parameters can influence the surface diffusion of these adsorbed molecules into the electron beam where they are deposited in the form of long chain carbon compounds by interaction with the primary electrons.

Blue Sapphire with Partial Red Surface Diffusion

2020 ◽  
Vol 37 (1) ◽  
pp. 23-24
Author(s):  
Bear Williams ◽  
Cara Williams ◽  
Charles I. Carmona
Keyword(s):  
Surface Diffusion

Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint

2004 ◽  
Author(s):  
Norman J. Armendariz ◽  
Prawin Paulraj
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Gold Surface ◽  
Circuit Board ◽  
Lead Free ◽  
Processing Temperature ◽  
The European Union ◽  
Printed Circuit ◽  
Higher Temperature ◽  
Tin Silver Copper

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

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