scholarly journals Chemical plating

2020 ◽  
Vol 98 (6) ◽  
pp. 48-48
Keyword(s):  
Chemical Plating

scholarly journals Removal of Phenol from Aqueous Solution Using Internal Microelectrolysis with Fe-Cu: Optimization and Application on Real Coking Wastewater

Processes ◽  
2021 ◽  
Vol 9 (4) ◽  
pp. 720
Author(s):  
Do Tra Huong ◽  
Nguyen Van Tu ◽  
Duong Thi Tu Anh ◽  
Nguyen Anh Tien ◽  
Tran Thi Kim Ngan ◽  
...  
Keyword(s):  
Aqueous Solution ◽  
Ph Value ◽  
Reaction Rate Constant ◽  
Phenol Concentration ◽  
Treated Wastewater ◽  
Coking Wastewater ◽  
X Ray ◽  
Chemical Plating ◽  
Internal Electrolysis ◽  
Phenol Decomposition

Fe-Cu materials were synthesized using the chemical plating method from Fe powder and CuSO4 5% solution and then characterized for surface morphology, composition and structure by scanning electron microscopy (SEM), energy dispersive X-ray spectroscopy (EDS) and X-ray diffraction (XRD), respectively. The as-synthesized Fe-Cu material was used for removal of phenol from aqueous solution by internal microelectrolysis. The internal electrolysis-induced phenol decomposition was then studied with respect to various parameters such as pH, time, Fe-Cu material weight, phenol concentration and shaking speed. The optimal phenol decomposition (92.7%) was achieved under the conditions of (1) a pH value of phenol solution of 3, (2) 12 h of shaking at the speed of 200 rpm, (3) Fe-Cu material weight of 10 g/L, (4) initial phenol concentration of 100.98 mg/L and (5) at room temperature (25 ± 0.5 °C). The degradation of phenol using Fe-Cu materials obeyed the second-order apparent kinetics equation with a reaction rate constant of k of 0.009 h−1L mg−1. The optimal process was then tested against real coking wastewater samples, resulting in treated wastewater with favorable water indicators. Current findings justify the use of Fe-Cu materials in practical internal electrolysis processes.

scholarly journals On Control of Chemical Plating Bath (No. 2)

1961 ◽  
Vol 12 (3) ◽  
pp. 83-85
Author(s):  
Boshin Ro ◽  
Shigeomi Matsumoto
Keyword(s):  
Plating Bath ◽  
Chemical Plating

The Influences of the Plating’s Hardness, Abrasion and Antifriction Property Caused by the Adding of Nano- Al2O3 and PTFE

2012 ◽  
Vol 557-559 ◽  
pp. 1683-1686 ◽  
Author(s):  
Xiao Feng Xu ◽  
Wen Bin Yao ◽  
Jiu Hua Xu ◽  
Wei Zhang ◽  
Lin Yang ◽  
...  
Keyword(s):  
Wear Resistance ◽  
Antifriction Property ◽  
Chemical Plating ◽  
Composite Plating ◽  
Plating Solution ◽  
Alloy Plating

Composite plating Ni-P-PTFE- nano- Al2O3was made by adding nano-scaled Al2O3and PTFE into chemical plating Ni-P alloy plating solution. The influences of the plating material’s hardness, abrasion and antifriction property caused by the additive amount of nano- Al2O3and PTFE were studied in the paper. The results indicate that the composite plating’s hardness, wear resistance and antifriction can be greatly improved by adding nano- Al2O3and PTFE into it.

Study of the Technology of Chemical Copper Plating on Al-CuO Agglomerated Powders

2007 ◽  
Vol 280-283 ◽  
pp. 591-592
Author(s):  
Jun Yan ◽  
Jian Zheng Yi ◽  
Hai Ping Cui ◽  
Xin Kang Du ◽  
Jian Jiang Wang
Keyword(s):  
Orthogonal Design ◽  
Copper Plating ◽  
Research Focus ◽  
Chemical Plating

This research focus on the technology of copper chemical plating on Al-CuO agglomerated powders with the size of 150-200µm. Orthogonal design is employed to gain the optimized formula, and the quality of the cladding was analyzed by means of SEM and EPMA. The results show that the cladding is uniform and the Al-CuO powders are primarily coated by copper.

Hardness and Corrosion Resistance of Ni/NiB Bi-Layer and Ni/NiB/NiB-PTFE Tri-Layer Coatings Prepared by Electrodeposition and Dynamic Chemical Plating (DCP) Techniques

2018 ◽  
Vol 165 (14) ◽  
pp. D753-D760 ◽  
Author(s):  
J. R. López ◽  
P. F. Méndez ◽  
J. J. Pérez-Bueno ◽  
G. Trejo ◽  
G. Stremsdoerfer ◽  
...  
Keyword(s):  
Corrosion Resistance ◽  
Chemical Plating

MICROWAVE ABSORBING PROPERTIES OF CO/REDUCED GRAPHENE OXIDE IN KU-BAND

2013 ◽  
Vol 06 (04) ◽  
pp. 1350042 ◽  
Author(s):  
SHUAI LIN ◽  
JINGHUA YU ◽  
FANGHUI WANG ◽  
YONGSHENG WEI ◽  
BAOGUO YUAN ◽  
...  
Keyword(s):  
Graphene Oxide ◽  
Reduced Graphene Oxide ◽  
Reflection Loss ◽  
Wide Frequency Range ◽  
Maximum Absorption ◽  
Frequency Range ◽  
Chemical Plating ◽  
Oxidation Reduction ◽  
Reduced Graphene ◽  
Plating Method

Reduced graphene oxide (RGO) was prepared by the oxidation-reduction method. Cobalt nanoparticles were coated on the surfaces of the graphene sheets by using a chemical plating method. The complex relative permittivity and permeability in the frequency range of 2–18 GHz were measured by using a vector network analyzer. The reflection loss curves of the materials were calculated using computer simulation. The simulated results showed that the reflection loss of Co /RGO was stronger than that of RGO. The maximum absorption peaks shifted to lower frequency region as the thickness increased. The reflection loss greater than -10 dB over a wide frequency range 12.5–17.5 GHz and the maximum absorption peak was -12.5 dB at 15.5 GHz at a thickness of 2 mm.

The Research of Spraying SiC/Cu Electronic Packaging Composites

2011 ◽  
Vol 284-286 ◽  
pp. 620-623
Author(s):  
Ming Hu ◽  
Jing Gao ◽  
Yun Long Zhang
Keyword(s):  
Thermal Conductivity ◽  
Thermal Expansion ◽  
Process Parameters ◽  
Electronic Packaging ◽  
High Speed ◽  
Volume Fraction ◽  
Flame Spraying ◽  
Packaging Materials ◽  
Excellent Performance ◽  
Chemical Plating

The SiC/Cu electronic packaging composites with excellent performance were successfully prepared by the chemical plating copper on the surface of SiC powders and high-speed flame spraying technology. The results showed that the homogeneous dense coated layers can be obtained on the surface of SiC powder by optimizing process parameters. The volume fraction of SiC powders in the composites could significantly increase and figure was beyond 55vol% after spraying Copper. The SiC and Cu were the main phases in the spraying SiC/Cu electronic packaging composite, at the same time Cu2O can be tested as the trace phase. The interface combination properties of SiC/Cu in the hot-pressed samples can obviously improve. The thermal expansion coefficient and thermal conductivity of SiC/Cu electronic packaging composite basic can satisfy the requirements for electronic packaging materials.

Stacking of Known Good Rebuilt Wafers without TSV - Applications to Memories and SiP

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 002020-002074
Author(s):  
Christian Val ◽  
Pascal Couderc ◽  
Pierre Lartigues
Keyword(s):  
Reduction Factor ◽  
Wafer Level ◽  
Aircraft Structure ◽  
Adhesive Film ◽  
Chemical Plating ◽  
Direct Laser ◽  
European Program ◽  
Development Agreement ◽  
Low Costs ◽  
Build System

The 3-D interconnection started at 3D PLUS in 1996 and led to the stacking of nearly all types of analogical and logical components, sensors, MEMS, etc for the Hi-Rel field (Space, Defence, Medical, Industrial). This technology is extremely robust (−130°C +175°C, 40000g), and is fully qualified by all worldwide most important Space Agencies and for Defence applications. A technological break started in 2002 ; It consisted in another 20 to 30 reduction factor of the weight and volume of these 3-D modules.The Z pitch is 100μm and the X Y size is given by the size of the larger die plus 100μm of polymer around it. This is a stacked of Known Good Rebuilt Wafer of full wafer level technique. The dice are received in wafers and following operations are carried out :- Pick, flip and place of the good dice on a “sticking skin”- Moulding of the whole of this « pseudo wafer » in order to obtain what we call a « Known Good Rebuilt Wafer (KGRW) ». These two first steps are already developed by Infineon and mainly Freescale (RCP technique up to 300mm)- Stacking and gluing of KGRW 1, 2, 3…, n, by means of an adhesive film- Dicing of these stacked rebuilt wafers by techniques identical to the dicing of standard wafers- Metallization of the dicing streets with nickel + gold by electroless chemical plating identical to the UBM plating technique- Direct laser patterning by laser with our edge connection technique up to 100μm pitch. Below this pitch, the Thru Polymer Via (TPV) are made through the stacked wafers. The equivalent pitch will be 20μm. it can be noticed that the shielding can be made on the dicing street.- Electrical test at the stacked wafer level- Singulation of the 3D modules This approach allows using standard dice without any modification. It is multi sources and the stacking of the good rebuilt wafers allows to get an excellent yield. A development agreement has been signed with a semiconductors manufacturer. A development is in progress with the most worldwide important manufacturer of smart cards in order to integrate 5 levels of dice (including a MEMS) within a cavity of 550 μm inside the 800μm SIM card. Other applications with MEMS will be presented:- “Abandoned Sensors” for Heath Monitoring of the aircraft structure developed during the European Program: “e-Cubes” ,- Gyroscope with 6 MEMS,- Micro camera for endoscopy…- Medical applications with an important development made for 3 major pacemaker manufacturers. This « full wafer level » approach will allow to build System in Package (SiP) or “Abandoned Sensors” at very low costs, since the process uses mainly the steps of wafers building; the “panelization” allows to be in parallel processing from A to Z steps. Moreover, the use of Known Good Rebuilt Wafer like the RCP allows stacking Good wafer at the reverse what is impossible with the wafer to wafer approach.

Stacking of Known Good Rebuilt Wafers without TSV - Industrial Applications

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001126-001174
Author(s):  
Christian Val ◽  
Pascal Couderc ◽  
Nadia Boulay
Keyword(s):  
Industrial Applications ◽  
Reduction Factor ◽  
Wafer Level ◽  
Adhesive Film ◽  
Chemical Plating ◽  
Direct Laser ◽  
D Modules ◽  
Development Agreement ◽  
Low Costs ◽  
Build System

The 3-D interconnection started at 3D PLUS in 1996 and led to the stacking of nearly all types of analogical and logical components, sensors, MEMS, etc for the Hi-Rel field (Space, Defence, Medical, Industrial). This technology is extremely robust (−130 °C +175 °C, 40000g), and is fully qualified by all worldwide most important Space Agencies, for Defence applications and Harsh environment. A technological break started in 2002 ; it consisted in another 20 to 30 reduction factor of the weight and volume of these 3-D modules. The Z pitch is 100 μm and the X Y size is given by the size of the larger die plus 100 μm of polymer around it. This is a stacked of Known Good Rebuilt Wafer of full wafer level technique. The dice are received in wafers and following operations are carried out :- Pick, flip and place of the good dice on a “sticking skin”- Moulding of the whole of this « pseudo wafer » in order to obtain what we call a « Known Good Rebuilt Wafer (KGRW) ». These two first steps are already developed by Freescale (RCP technique up to 300mm), then Infineon and Nanium (ex Infineon/Quimoda) and now about ten companies are developing this 2-D approach:- Stacking and gluing of KGRW 1, 2, 3..., n, by means of an adhesive film- Dicing of these stacked rebuilt wafers by techniques identical to the dicing of standard wafers- Metallization of the dicing streets with nickel + gold by electroless chemical plating identical to the UBM plating technique- Direct laser patterning by laser with our edge connection technique up to 100 μm pitch. Below this pitch, the Thru Polymer Via (TPV) are made through the stacked wafers. The equivalent pitch will be 20 μm. it can be noticed that the shielding can be made on the dicing street.- Electrical test at the stacked wafer level- Singulation This approach allows to use standard dice without any modification. It is multi sources and the stacking of the good rebuilt wafers allows to obtain an excellent yield. A development agreement has been signed with a semiconductors manufacturer. Smart card application- A development is in progress with the most worldwide important manufacturer of smart cards in order to integrate 5 levels of dice within a cavity of 550 μm inside the 800 μm SIM card. Medical applications will be presented:- Micro modulator with 5 ASICs within a 3 mm diameter tube,- Prototypes for the major US pacemaker manufacturer (Medtronic) and one European pacemaker manufacturer (Sorin/Ela Medical). A full pacemaker module of 0,5 cm3 (16 times smaller than the standard pacemaker: 8 cm3) will be shown- Micro camera for Hard X-Ray for Philips Medical (DE). Industrial applications- Abandoned sensors for Airbus and industrial areas. This « full wafer level » approach will allow to build System in Package (SiP) or “Abandoned Sensors” at very low costs, since the process uses mainly the steps of wafers building; the “panelization” allows to be in parallel processing from A to Z steps. Moreover, the use of Known Good Rebuilt Wafer like the RCP allows to stack Good wafer at the reverse what is impossible with the wafer to wafer approach.

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