Reliable Multistate Data Storage with Low Power Consumption by Selective Oxidation of Pyramid-Structured Resistive Memory

2017 ◽  
Vol 9 (44) ◽  
pp. 38643-38650 ◽  
Author(s):  
Youngjin Kim ◽  
Hanhyeong Choi ◽  
Hyun S. Park ◽  
Moon Sung Kang ◽  
Keun-Young Shin ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Selective Oxidation ◽  
Data Storage ◽  
Low Power Consumption ◽  
Resistive Memory

The Nature of Lithium-Ion Transport in Low Power Consumption LiFePO4 Resistive Memory with Graphite as Electrode

2018 ◽  
Vol 12 (10) ◽  
pp. 1800320 ◽  
Author(s):  
Lei Zhang ◽  
Cheng Wu ◽  
Jun Liu ◽  
Xiaoning Zhao ◽  
Zhongqiang Wang ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ion Transport ◽  
Lithium Ion ◽  
Low Power Consumption ◽  
Resistive Memory

Design and implementation of power and area optimized AES architecture on FPGA for IoT application

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Rajasekar P. ◽  
Mangalam H.
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Data Storage ◽  
Resource Sharing ◽  
Low Power Consumption ◽  
Multiplicative Inverse ◽  
Content Type ◽  
Field Programmable ◽  
Pipe Line ◽  
Affine Transforms

Purpose The growing trends in the usage of hand held devices necessitate the need to design them with low power consumption and less area design. Besides, information security is gaining enormous importance in information transmission and data storage technology. In addition, today’s technology world is connected, communicated and controlled via the Internet of Things (IoT). In many applications, the most standard and widely used cryptography algorithm for providing security is Advanced Encryption Standard (AES). This paper aims to design an efficient model of AES cryptography for low power and less area. Design/methodology/approach First, the main issues related to less area and low power consumption in the AES encryption core are addressed. To implement optimized AES core, the authors proposed optimized multiplicative inverse, affine transforms and Xtime multipliers functions, which are the core function of AES’s core. In addition, to achieve the high throughput, it uses the multistage pipeline and resource reuse architectures for SBox and Mixcolumn of AES. Findings The results of optimized AES architecture have revealed that the multistage pipe line and resource sharing are optimal design model in Field Programmable Gate Array (FPGA) implementation. It could provide high security with low power and area for IoT and wireless sensors networks. Originality/value This proposed optimized modified architecture has been implemented in FPGA to calculate the power, area and delay parameters. This multistage pipeline and resource sharing have promised to minimize the area and power.

Optimal design of a high homogeneous and small-size shim coil for atomic spin gyroscope based on 0-1 linear programming

2020 ◽  
Vol 64 (1-4) ◽  
pp. 165-172
Author(s):  
Dongge Deng ◽  
Mingzhi Zhu ◽  
Qiang Shu ◽  
Baoxu Wang ◽  
Fei Yang
Keyword(s):  
Linear Programming ◽  
Power Consumption ◽  
Low Power ◽  
Optimization Design ◽  
Structural Parameters ◽  
Axial Position ◽  
Low Power Consumption ◽  
Optimal Method ◽  
Atomic Spin ◽  
Shim Coil

It is necessary to develop a high homogeneous, low power consumption, high frequency and small-size shim coil for high precision and low-cost atomic spin gyroscope (ASG). To provide the shim coil, a multi-objective optimization design method is proposed. All structural parameters including the wire diameter are optimized. In addition to the homogeneity, the size of optimized coil, especially the axial position and winding number, is restricted to develop the small-size shim coil with low power consumption. The 0-1 linear programming is adopted in the optimal model to conveniently describe winding distributions. The branch and bound algorithm is used to solve this model. Theoretical optimization results show that the homogeneity of the optimized shim coil is several orders of magnitudes better than the same-size solenoid. A simulation experiment is also conducted. Experimental results show that optimization results are verified, and power consumption of the optimized coil is about half of the solenoid when providing the same uniform magnetic field. This indicates that the proposed optimal method is feasible to develop shim coil for ASG.

An Ultra-low Power Consumption MAC Protocol Complied with IEEE 802.15.4/4e for Wireless Smart Utility Networks

2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Mac Protocol ◽  
Low Power Consumption ◽  
Ultra Low Power

scholarly journals Ultra Low Power Consumption for Self-Oscillating Nanoelectromechanical Systems Constructed by Contacting Two Nanowires

Nano Letters ◽  
2013 ◽  
Vol 13 (4) ◽  
pp. 1451-1456 ◽  
Author(s):  
T. Barois ◽  
A. Ayari ◽  
P. Vincent ◽  
S. Perisanu ◽  
P. Poncharal ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Nanoelectromechanical Systems ◽  
Low Power Consumption ◽  
Ultra Low Power
Sign in / Sign up

Export Citation Format

Share Document