Novel Self-Heated Gas Sensors Using on-Chip Networked Nanowires with Ultralow Power Consumption

2017 ◽  
Vol 9 (7) ◽  
pp. 6153-6162 ◽  
Author(s):  
Ha Minh Tan ◽  
Chu Manh Hung ◽  
Trinh Minh Ngoc ◽  
Hugo Nguyen ◽  
Nguyen Duc Hoa ◽  
...  
Keyword(s):  
Power Consumption ◽  
Gas Sensors ◽  
Ultralow Power ◽  
On Chip

scholarly journals Nanomaterials make possible integrating gas sensors in wireless and ultralow power consumption motes

2011 ◽  
Vol 25 ◽  
pp. 1053-1056
Author(s):  
J. Llosa ◽  
M. Martínez de Marigorta ◽  
J. Bécares ◽  
O. Monereo ◽  
J.D. Prades ◽  
...  
Keyword(s):  
Power Consumption ◽  
Gas Sensors ◽  
Ultralow Power

Ultralow power consumption gas sensors based on self-heated individual nanowires

2008 ◽  
Vol 93 (12) ◽  
pp. 123110 ◽  
Author(s):  
J. D. Prades ◽  
R. Jimenez-Diaz ◽  
F. Hernandez-Ramirez ◽  
S. Barth ◽  
A. Cirera ◽  
...  
Keyword(s):  
Power Consumption ◽  
Gas Sensors ◽  
Ultralow Power

Micromachined Nanoparticulate Ceramic Gas Sensor Array on Mems Substrates

2001 ◽  
Vol 687 ◽  
Author(s):  
Martin Heule ◽  
Ludwig J. Gauckler
Keyword(s):  
Thin Film ◽  
Power Consumption ◽  
Gas Sensors ◽  
Tin Oxide ◽  
Soft Lithography ◽  
Sensor Array ◽  
Gas Sensing ◽  
Processing Parameters ◽  
High Specific Surface Area ◽  
On Chip

AbstractIn most MEMS applications, dust and particles are avoided with considerable endeavor. However, for many applications such as gas sensors, powders of functional ceramics would often provide better performance than corresponding thin film layers. There are abundant ways to synthesize powders with well defined chemical composition, phase and size distribution, whereas the processing parameters for thin-film preparation often are limited. Specifically where the functionality is based on a chemical reaction on surfaces, nanoscaled powders with a high specific surface area have proven useful. This is the case for tin oxide gas sensors that exhibit a drop in electrical resistivity induced by the combustion of the analyte gas. Soft lithography was used for the fabrication of mesoscaled powder-based ceramic structures. In this paper, we present the integration of small tin oxide microstructures with an effective gas-sensing area of 10 by 30 νm2 on a micro-hotplate substrate. Such a substrate can heat the ceramic sensor to operating temperatures quickly with low power consumption. A whole array of sensors can be integrated on one micro-hotplate. Processing steps to prepare the sensor array on the micro hot plate are presented and discussed concerning processing sequence, sensitivity towards 1000 to 1500 ppm hydrogen and power consumption. Additionally, effects of grain growth due to on-chip annealing of the ceramic nanostructure were observed.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals Ultracompact and low-power-consumption silicon thermo-optic switch for high-speed data

Nanophotonics ◽  
2020 ◽  
Vol 10 (2) ◽  
pp. 937-945
Author(s):  
Ruihuan Zhang ◽  
Yu He ◽  
Yong Zhang ◽  
Shaohua An ◽  
Qingming Zhu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
High Performance ◽  
Pulse Amplitude ◽  
Telecommunication Networks ◽  
Low Power Consumption ◽  
Power Efficient ◽  
High Speed Data ◽  
On Chip

AbstractUltracompact and low-power-consumption optical switches are desired for high-performance telecommunication networks and data centers. Here, we demonstrate an on-chip power-efficient 2 × 2 thermo-optic switch unit by using a suspended photonic crystal nanobeam structure. A submilliwatt switching power of 0.15 mW is obtained with a tuning efficiency of 7.71 nm/mW in a compact footprint of 60 μm × 16 μm. The bandwidth of the switch is properly designed for a four-level pulse amplitude modulation signal with a 124 Gb/s raw data rate. To the best of our knowledge, the proposed switch is the most power-efficient resonator-based thermo-optic switch unit with the highest tuning efficiency and data ever reported.

scholarly journals Exploring a New Adaptive Routing Based on the Dijkstra Algorithm in Optical Networks-on-Chip

Micromachines ◽  
2021 ◽  
Vol 12 (1) ◽  
pp. 54
Author(s):  
Yan-Li Zheng ◽  
Ting-Ting Song ◽  
Jun-Xiong Chai ◽  
Xiao-Ping Yang ◽  
Meng-Meng Yu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Power Control ◽  
Optical Networks ◽  
Output Power ◽  
Network Performance ◽  
Transmission Loss ◽  
Adaptive Routing ◽  
Dijkstra Algorithm ◽  
Networks On Chip ◽  
On Chip

The photoelectric hybrid network has been proposed to achieve the ultrahigh bandwidth, lower delay, and less power consumption for chip multiprocessor (CMP) systems. However, a large number of optical elements used in optical networks-on-chip (ONoCs) generate high transmission loss which will influence network performance severely and increase power consumption. In this paper, the Dijkstra algorithm is adopted to realize adaptive routing with minimum transmission loss of link and reduce the output power of the link transmitter in mesh-based ONoCs. The numerical simulation results demonstrate that the transmission loss of a link in optimized power control based on the Dijkstra algorithm could be maximally reduced compared with traditional power control based on the dimensional routing algorithm. Additionally, it has a greater advantage in saving the average output power of optical transmitter compared to the adaptive power control in previous studies, while the network size expands. With the aid of simulation software OPNET, the network performance simulations in an optimized network revealed that the end-to-end (ETE) latency and throughput are not vastly reduced in regard to a traditional network. Hence, the optimized power control proposed in this paper can greatly reduce the power consumption of s network without having a big impact on network performance.

scholarly journals 1.0 V-0.18 µm CMOS Tunable Low Pass Filters with 73 dB DR for On-Chip Sensing Acquisition Systems

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 563
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Low Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Active Area ◽  
Current Steering ◽  
Low Pass ◽  
On Chip ◽  
Low Pass Filters

This paper presents a new approach based on the use of a Current Steering (CS) technique for the design of fully integrated Gm–C Low Pass Filters (LPF) with sub-Hz to kHz tunable cut-off frequencies and an enhanced power-area-dynamic range trade-off. The proposed approach has been experimentally validated by two different first-order single-ended LPFs designed in a 0.18 µm CMOS technology powered by a 1.0 V single supply: a folded-OTA based LPF and a mirrored-OTA based LPF. The first one exhibits a constant power consumption of 180 nW at 100 nA bias current with an active area of 0.00135 mm2 and a tunable cutoff frequency that spans over 4 orders of magnitude (~100 mHz–152 Hz @ CL = 50 pF) preserving dynamic figures greater than 78 dB. The second one exhibits a power consumption of 1.75 µW at 500 nA with an active area of 0.0137 mm2 and a tunable cutoff frequency that spans over 5 orders of magnitude (~80 mHz–~1.2 kHz @ CL = 50 pF) preserving a dynamic range greater than 73 dB. Compared with previously reported filters, this proposal is a competitive solution while satisfying the low-voltage low-power on-chip constraints, becoming a preferable choice for general-purpose reconfigurable front-end sensor interfaces.

On‐Chip Tailorability of Capacitive Gas Sensors Integrated with Metal–Organic Framework Films

2019 ◽  
Vol 58 (40) ◽  
pp. 14089-14094 ◽  
Author(s):  
Hongye Yuan ◽  
Jifang Tao ◽  
Nanxi Li ◽  
Avishek Karmakar ◽  
Chunhua Tang ◽  
...  
Keyword(s):  
Gas Sensors ◽  
Metal Organic Framework ◽  
Metal Organic ◽  
On Chip ◽  
Organic Framework

scholarly journals Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 346 ◽  
Author(s):  
Lili Shen ◽  
Ning Wu ◽  
Gaizhen Yan
Keyword(s):  
Power Consumption ◽  
Thermal Management ◽  
System Performance ◽  
Control Policy ◽  
Three Dimension ◽  
Processor Core ◽  
Management Scheme ◽  
And Performance ◽  
On Chip ◽  
Silicon Vias

By using through-silicon-vias (TSV), three dimension integration technology can stack large memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory access and enhance system performance. However, the integration of more on-chip caches increases chip power density, which might lead to temperature-related issues in power consumption, reliability, cooling cost, and performance. An effective thermal management scheme is required to ensure the performance and reliability of the system. In this study, a fuzzy-based thermal management scheme (FBTM) is proposed that simultaneously considers cores and stacked caches. The proposed method combines a dynamic cache reconfiguration scheme with a fuzzy-based control policy in a temperature-aware manner. The dynamic cache reconfiguration scheme determines the size of the cache for the processor core according to the application that reaches a substantial amount of power consumption savings. The fuzzy-based control policy is used to change the frequency level of the processor core based on dynamic cache reconfiguration, a process which can further improve the system performance. Experiments show that, compared with other thermal management schemes, the proposed FBTM can achieve, on average, 3 degrees of reduction in temperature and a 41% reduction of leakage energy.

Multi-level phase-change memory with ultralow power consumption and resistance drift

2021 ◽  
Author(s):  
Bin Liu ◽  
Kaiqi Li ◽  
Wanliang Liu ◽  
Jian Zhou ◽  
Liangcai Wu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Phase Change ◽  
Phase Change Memory ◽  
Multi Level ◽  
Ultralow Power ◽  
Change Memory
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