Reprogrammable Logic Gate and Logic Circuit Based on Multistimuli-Responsive Raspberry-like Micromotors

2016 ◽  
Vol 8 (24) ◽  
pp. 15654-15660 ◽  
Author(s):  
Lina Zhang ◽  
Hui Zhang ◽  
Mei Liu ◽  
Bin Dong
Keyword(s):  
2015 ◽  
Vol 51 (92) ◽  
pp. 16565-16568 ◽  
Author(s):  
Samuel J. Bradberry ◽  
Joseph P. Byrne ◽  
Colin P. McCoy ◽  
Thorfinnur Gunnlaugsson

Non-covalent incorporation of responsive luminescent lanthanide into a polymer gel produces three-output logic circuit with significant naked-eye colour changes.


2017 ◽  
Vol 140 ◽  
pp. 460-468 ◽  
Author(s):  
Changlin Zhao ◽  
Zhiqiang Wang ◽  
Xueqing Gong ◽  
Qisong Zhang ◽  
Chengyun Wang ◽  
...  

Author(s):  
Mohammad Zulkarnain O. ◽  
Amar Faiz Z.A. ◽  
Syahrul Hisham M. ◽  
Nur Dalila K.A. ◽  
N. Ismail

To supplement conventional teaching methods, use of new technology have recently being adapted in the current education system. Such examples are implementing simulators and quiz kits in a classroom session to assist teachers in providing standardized evaluation or practical and more direct examples of concepts that are being taught. Additionally, the well-known issue of attracting student interest in a so-called uninteresting conventional lecture may be solved by using this technological method. The objective of this works to provide methods on developing a prototype training kit (named as e-Logic trainer kit or e-LTK) which comprises of an electronic simulator and quiz assessment module to evaluate subject knowledge on logic gates. The e-LTK is developed by using Arduino Mega 2560 as the base microcontroller, equipped with keypad and display module as the user input/output interface. The quiz assessment module contained in the prototype also allows conversion of inputs by combinatorial logic circuits into output in the form of timing diagram. This equipment enables electrical engineering students to simulate several combinations of logic circuit, reinforcing the understanding of logic circuit operation. The effectiveness of using this prototype in educational settings have been evaluated through a survey on students and instructors at Faculty of Technology in Engineering (FTK) in Universiti Teknikal Malaysia Melaka (UTeM). Response has been positive, with 60% of the correspondence has shown positive feedbacks, indicating the usefulness of the prototype kit.


2020 ◽  
Author(s):  
Lane Yoder

AbstractThe stomatogastric ganglion (STG) is a group of about 30 neurons that resides on the stomach in decapod crustaceans. Its two central pattern generators (CPGs) control the chewing action of the gastric mill and the peristaltic movement of food through the pylorus to the gut. The STG has been studied extensively because it has properties that are common to all nervous systems and because of the small number of neurons and other features that make it convenient to study. So many details are known that the STG is considered a classic test case in neuroscience for the reductionist strategy of explaining the emergence of macro-level phenomena from micro-level data. In spite of the intense scrutiny the STG has received, how it generates its rhythmic patterns of bursts remains unknown.The novel neural networks presented here model the pyloric CPG of the American lobster (Homarus americanus). Each model’s connectivity is explicit, and its operation depends only on minimal neuron capabilities of excitation and inhibition. One type of model CPGs, flip-flop ring oscillators, is apparently new to engineering, making it an example of neuroscience and logic circuit design informing each other. Several testable predictions are given here, and STG phenomena are shown to support several predictions of neural flip-flops that were given in a previous paper on short-term memory.The model CPGs are not the same as the more complex pyloric CPG. But they show how neurons can be connected to produce oscillations, and there are enough similarities in significant features that they may be considered first approximations, or perhaps simplified versions, of STG architecture. The similarities include 1) mostly inhibitory synapses; 2) pairs of cells with reciprocal, inhibitory inputs, complementary outputs that are approximately 180 degrees out of phase, and state changes occurring with the high output changing first; 3) cells that have reciprocal, inhibitory inputs with more than one other cell; and 4) six cells that produce coordinated oscillations with the same period, four phases distributed approximately uniformly over the period, and half of the burst durations approximately 1/4 of the period and the other half 3/8. These variables cannot be controlled independently in the design, suggesting a similar architecture in the models and the STG.Some of the neural network designs can be derived from electronic logic circuit designs simply by moving each negation symbol from one end of a connection to the other. This does not change the logic of the network, but it changes each logic gate to one that can be implemented with a single neuron.


The Analyst ◽  
2020 ◽  
Vol 145 (20) ◽  
pp. 6572-6578
Author(s):  
Xun Zhang ◽  
Qiang Zhang ◽  
Yuan Liu ◽  
Xiaopeng Wei

A switchable logic circuit which can represent three kinds of logical operations by adjusting concentration of silver ion and cysteine (Cys) based on E6 and Ag10c DNAzyme was developed.


2020 ◽  
Vol 15 (3) ◽  
pp. 404-414
Author(s):  
Jun-Wei Sun ◽  
Yu-Qi Tian ◽  
Yan-Feng Wang

The logic function based on memristor has been proved and can be applied to the future large scale integrated circuits. In this paper, we use logic circuit based on memristor to realize the function of eight-person voter. The basic logic circuit designed in this paper is consisted of two Hewlett-Packard memristors in series connection and an operational amplifier. Operational amplifiers are used to regulate the output voltages to meet the requirements of the input signals in the next stage circuits. The adder, binary comparator and multi-input logic gate are realized by using the designed logic circuit. Full adders, binary comparators and multi-input logic gates are combined into eight-person voter circuit. Theoretical analysis and spice simulation results verify the feasibility of the circuit under different cases. This method is expected to be applied to more complex voter logic circuits based on memristor.


2005 ◽  
Vol 15 (03) ◽  
pp. 223-235
Author(s):  
GARIMELLA RAMA MURTHY

A mathematical model of an arbitrary multi-dimensional neural network is developed and a convergence theorem for an arbitrary multi-dimensional neural network represented by a fully symmetric tensor is stated and proved. The input and output signal states of a multi-dimensional neural network/logic gate are related through an energy function, defined over the fully symmetric tensor (representing the connection structure of a multi-dimensional neural network). The inputs and outputs are related such that the minimum/maximum energy states correspond to the output states of the logic gate/neural network realizing a logic function. Similarly, a logic circuit consisting of the interconnection of logic gates, represented by a block symmetric tensor, is associated with a quadratic/higher degree energy function. Infinite dimensional logic theory is discussed through the utilization of infinite dimension/order tensors.


2021 ◽  
Author(s):  
Lokesh B ◽  
Sai Pavan kumar K ◽  
Pown M ◽  
Lakshmi B

Abstract This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 103 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 103 times and less propagation delay than that of hetero-junction NOR logic circuit


Sign in / Sign up

Export Citation Format

Share Document