Task mapping and scheduling for network-on-chip based multi-core platform with transient faults

2018 ◽  
Vol 83 ◽  
pp. 34-56 ◽  
Author(s):  
Navonil Chatterjee ◽  
Suraj Paul ◽  
Santanu Chattopadhyay
Keyword(s):  
Network On Chip ◽  
Task Mapping ◽  
Transient Faults ◽  
On Chip

scholarly journals Genetic algorithm for task mapping in embedded systems on a hierarchical architecture based on wireless network on chip WiNoC

DYNA ◽  
2017 ◽  
Vol 84 (201) ◽  
pp. 202 ◽  
Author(s):  
Maribell Sacanamboy Franco ◽  
Freddy Bolaños-Martinez ◽  
Álvaro Bernal-Noreña ◽  
Rubén Nieto-Londoño
Keyword(s):  
Genetic Algorithm ◽  
Embedded Systems ◽  
Wireless Network ◽  
Network On Chip ◽  
Hierarchical Architecture ◽  
Task Mapping ◽  
On Chip ◽  
La Red

Los sistemas de red en chip (NoC) fueron desarrollados originalmente para proporcionar un alto rendimiento, mediante la disponibilidad de varias unidades de procesamiento, conectadas a través de una red cableada dentro del circuito integrado. Wireless NoC (WiNoC o WNoC) son una evolución natural de los sistemas NoC, que integran una comunicación jerárquica dentro del chip para mejorar la escalabilidad. El mapeo de tareas en los sistemas WNoC representa un proceso desafiante, que a menudo implica varios objetivos de optimización, como potencia, rendimiento, productividad, uso de recursos y métricas de red. Este artículo describe un algoritmo genético basado en un enfoque para encontrar soluciones óptimas de asignación de tareas en tiempo de diseño, para sistemas embebidos que trabajan sobre un WiNoC. Los objetivos de optimización fueron: Aceleración, Consumo de Energía y Ancho de Banda. La red de destino utilizada para la simulación puede ser vista como un WiNoC jerárquica de dos niveles. El primer nivel corresponde a un conjunto de subredes que están conectadas por cables y son de tipo malla. El segundo nivel corresponde a una topología en estrella de enlaces inalámbricos, que conectan las subredes de primer nivel. El algoritmo propuesto muestra un buen desempeño en relación con los objetivos de optimización y la WiNoC heterogéneo simulada.

scholarly journals Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip

2018 ◽  
Vol 67 (12) ◽  
pp. 1818-1834 ◽  
Author(s):  
Weichen Liu ◽  
Lei Yang ◽  
Weiwen Jiang ◽  
Liang Feng ◽  
Nan Guan ◽  
...  
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Multiprocessor System ◽  
Task Mapping ◽  
Dynamically Reconfigurable ◽  
On Chip

scholarly journals Static and dynamic task mapping onto network on chip multiprocessors

DYNA ◽  
2014 ◽  
Vol 81 (185) ◽  
pp. 28 ◽  
Author(s):  
Freddy Bolaños-Martínez ◽  
Jose Edison Aedo ◽  
Fredy Rivera-Vélez
Keyword(s):  
Chip Multiprocessors ◽  
Network On Chip ◽  
Task Mapping ◽  
Dynamic Task ◽  
On Chip

Dynamic task mapping for Network-on-Chip based systems

2015 ◽  
Vol 61 (7) ◽  
pp. 293-306 ◽  
Author(s):  
Tahir Maqsood ◽  
Sabeen Ali ◽  
Saif U.R. Malik ◽  
Sajjad A. Madani
Keyword(s):  
Network On Chip ◽  
Task Mapping ◽  
Dynamic Task ◽  
On Chip

Thermal and power aware task mapping on 3D Network on Chip

2016 ◽  
Vol 51 ◽  
pp. 157-167 ◽  
Author(s):  
Amin Mosayyebzadeh ◽  
Maziar Mehdizadeh Amiraski ◽  
Shaahin Hessabi
Keyword(s):  
Network On Chip ◽  
Task Mapping ◽  
3D Network ◽  
On Chip

A low-power task mapping method for network on chip

2015 ◽  
Author(s):  
Wenwen Cao ◽  
Wei Hu ◽  
Puzhang Wang ◽  
Mengke Song ◽  
Ruomiao Li
Keyword(s):  
Low Power ◽  
Mapping Method ◽  
Network On Chip ◽  
Task Mapping ◽  
On Chip

scholarly journals Tolerating Permanent Faults in the Input Port of the Network on Chip Router

2019 ◽  
Vol 9 (1) ◽  
pp. 11 ◽  
Author(s):  
Hala Mohammed ◽  
Wameedh Flayyih ◽  
Fakhrul Rokhani
Keyword(s):  
Network Performance ◽  
Deep Submicron ◽  
Network On Chip ◽  
Input Port ◽  
Virtual Channel ◽  
Transient Faults ◽  
Single Chip ◽  
Permanent Faults ◽  
Hardware Redundancy ◽  
On Chip

Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.

scholarly journals Task mapping and mesh topology exploration for an FPGA-based network on chip

2015 ◽  
Vol 39 (3) ◽  
pp. 189-199 ◽  
Author(s):  
Ke Pang ◽  
Virginie Fresse ◽  
Suying Yao ◽  
Otavio Alcantara De Lima
Keyword(s):  
Network On Chip ◽  
Task Mapping ◽  
Mesh Topology ◽  
On Chip
Sign in / Sign up

Export Citation Format

Share Document