Synergistic design of an application-oriented sparse directory on many-core embedded systems

BlueVisor: A Scalable Real-Time Hardware Hypervisor for Many-Core Embedded Systems

2018 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS) ◽

10.1109/rtas.2018.00013 ◽

2018 ◽

Cited By ~ 6

Author(s):

Zhe Jiang ◽

Neil C Audsley ◽

Pan Dong

Keyword(s):

Embedded Systems ◽

Real Time ◽

Many Core

Download Full-text

Optimistic Modeling and Simulation of Complex Hardware Platforms and Embedded Systems on Many-Core HPC Clusters

IEEE Transactions on Parallel and Distributed Systems ◽

10.1109/tpds.2018.2860014 ◽

2019 ◽

Vol 30 (2) ◽

pp. 428-444

Author(s):

Alireza Poshtkohi ◽

M. B. Ghaznavi-Ghoushchi ◽

Kamyar Saghafi

Keyword(s):

Embedded Systems ◽

Modeling And Simulation ◽

Many Core ◽

Hardware Platforms

Download Full-text

MPI hardware framework for many-core based embedded systems

International Journal of Sensor Networks ◽

10.1504/ijsnet.2021.112888 ◽

2021 ◽

Vol 35 (1) ◽

pp. 42

Author(s):

Rodrigo Vinicius Mendonça Pereira ◽

Laio Oriel Seman ◽

Marcelo Daniel Berejuck ◽

Douglas Rossi De Melo ◽

Analucia Schiaffino Morales ◽

...

Keyword(s):

Embedded Systems ◽

Many Core

Download Full-text

Optimized System-Level Design Methods for NoC-Based Many Core Embedded Systems

Advances in Systems Analysis, Software Engineering, and High Performance Computing - Handbook of Research on Embedded Systems Design ◽

10.4018/978-1-4666-6194-3.ch007 ◽

2014 ◽

pp. 150-179

Author(s):

Haoyuan Ying ◽

Klaus Hofmann ◽

Thomas Hollstein

Keyword(s):

Embedded Systems ◽

Design Optimization ◽

Optimization Methods ◽

Design Methods ◽

System Level ◽

System Level Design ◽

Level Design ◽

On Chip ◽

Many Core

Due to the growing demand on high performance and low power in embedded systems, many core architectures are proposed the most suitable solutions. While the design concentration of many core embedded systems is switching from computation-centric to communication-centric, Network-on-Chip (NoC) is one of the best interconnect techniques for such architectures because of the scalability and high communication bandwidth. Formalized and optimized system-level design methods for NoC-based many core embedded systems are desired to improve the system performance and to reduce the power consumption. In order to understand the design optimization methods in depth, a case study of optimizing many core embedded systems based on 3-Dimensional (3D) NoC with irregular vertical link distribution topology through task mapping, core placement, routing, and topology generation is demonstrated in this chapter. Results of cycle-accurate simulation experiments prove the validity and efficiency of the design methods. Specific to the case study configuration, in maximum 60% vertical links can be saved while maintaining the system efficiency in comparison to full vertical link connection 3D NoCs by applying the design optimization methods.

Download Full-text