Formal approach to agent-based dynamic reconfiguration in Networks-On-Chip

2013 ◽  
Vol 59 (9) ◽  
pp. 709-728 ◽  
Author(s):  
Sergey Ostroumov ◽  
Leonidas Tsiopoulos ◽  
Juha Plosila ◽  
Kaisa Sere
Keyword(s):  
Dynamic Reconfiguration ◽  
Formal Approach ◽  
Networks On Chip ◽  
Agent Based ◽  
On Chip

scholarly journals A Formal Approach to the Verification of Networks on Chip

2009 ◽  
Vol 2009 (1) ◽  
pp. 548324 ◽  
Author(s):  
Dominique Borrione ◽  
Amr Helmy ◽  
Laurence Pierre ◽  
Julien Schmaltz
Keyword(s):  
Formal Approach ◽  
Networks On Chip ◽  
On Chip

Hierarchical Agent-Based Monitoring Systems for Dynamic Reconfiguration in NoC Platforms

2014 ◽  
pp. 302-333
Author(s):  
Sergey Ostroumov ◽  
Leonidas Tsiopoulos ◽  
Marina Waldén ◽  
Juha Plosila
Keyword(s):  
Management System ◽  
Dynamic Reconfiguration ◽  
Network On Chip ◽  
Dynamic Monitoring ◽  
Monitoring Systems ◽  
Agent Based ◽  
Mechanism Of Decomposition ◽  
Construction Specification ◽  
On Chip ◽  
Many Core

A Network-On-Chip is a paradigm that tackles limitations of traditional bus-based interconnects. It allows complex applications that demand many resources to be deployed on many-core platforms effectively. To satisfy requirements on dependability, however, a NoC platform requires dynamic monitoring and reconfiguration mechanisms. In this chapter, the authors propose an agent-based management system that monitors the state of the platform and applies various reconfiguration techniques. These techniques aim at enabling uninterruptable execution of applications satisfying dependability requirements. The authors develop the proposed system within Event-B that provides a means for stepwise and correct-by-construction specification supported by mathematical proofs. Furthermore, the authors show the mechanism of decomposition of Event-B specifications such that a well-structured and hierarchical agent-based management system is derived.

scholarly journals Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures

2010 ◽  
Vol 2010 ◽  
pp. 1-15 ◽  
Author(s):  
Ludovic Devaux ◽  
Sana Ben Sassi ◽  
Sebastien Pillement ◽  
Daniel Chillet ◽  
Didier Demigny
Keyword(s):  
Interconnection Networks ◽  
Interconnection Network ◽  
Dynamic Reconfiguration ◽  
Computation Time ◽  
Reconfigurable Architectures ◽  
Partial Reconfiguration ◽  
Dynamic Management ◽  
Networks On Chip ◽  
Communication Architectures ◽  
On Chip

The dynamic and partial reconfiguration of FPGAs enables the dynamic placement in reconfigurable zones of the tasks that describe an application. However, the dynamic management of the tasks impacts the communications since tasks are not present in the FPGA during all computation time. So, the task manager should ensure the allocation of each new task and their interconnection which is performed by a flexible interconnection network. In this article, various communication architectures, in particular interconnection networks, are studied. Each architecture is evaluated with respect to its suitability for the paradigm of the dynamic and partial reconfiguration in FPGA implementations. This study leads us to propose the DRAFT network that supports the communication constraints into the context of dynamic reconfiguration. We also present DRAGOON, the automatic generator of networks, which allows to implement and to simulate the DRAFT topology. Finally, DRAFT and the two most popular Networks-on-Chip are implemented in several configurations using DRAGOON, and compared considering real implementation results.

Energy-Performance Analysis and Optimization for Networks-on-Chip

2014 ◽  
Vol 36 (5) ◽  
pp. 988-1003 ◽  
Author(s):  
Shuai ZHANG ◽  
Feng-Long SONG ◽  
Dong WANG ◽  
Zhi-Yong LIU ◽  
Dong-Rui FAN
Keyword(s):  
Performance Analysis ◽  
Energy Performance ◽  
Networks On Chip ◽  
On Chip

scholarly journals Ray Tracing Modeling of Electromagnetic Propagation for On-Chip Wireless Optical Communications

2018 ◽  
Vol 8 (4) ◽  
pp. 39 ◽  
Author(s):  
Franco Fuschini ◽  
Marina Barbiroli ◽  
Marco Zoli ◽  
Gaetano Bellanca ◽  
Giovanna Calò ◽  
...  
Keyword(s):  
Ray Tracing ◽  
Path Loss ◽  
Wireless Channel ◽  
Electromagnetic Propagation ◽  
Networks On Chip ◽  
Spatial Properties ◽  
Radiation Properties ◽  
Wireless Optical Communications ◽  
On Chip ◽  
The Relationship

Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures. Optical wireless networks on-chip are therefore being considered as promising solutions to overcome the technological limits of wired interconnects. In this work, the spatial properties of the on-chip wireless channel are investigated through a ray tracing approach applied to a layered representation of the chip structure, highlighting the relationship between path loss, antenna positions and radiation properties.

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