Silicon-aware distributed switch architecture for on-chip networks

2013 ◽  
Vol 59 (7) ◽  
pp. 505-515 ◽  
Author(s):  
Antoni Roca ◽  
Carles Hernández ◽  
José Flich ◽  
Federico Silla ◽  
José Duato
Keyword(s):  
Switch Architecture ◽  
On Chip

Wearout and Variation Tolerant Source Synchronous Communication for GALS Network-on-Chip Design

2014 ◽  
pp. 399-419
Author(s):  
Alessandro Strano ◽  
Carles Hernández ◽  
Federico Silla ◽  
Davide Bertozzi
Keyword(s):  
Cost Effective ◽  
Internal Communication ◽  
Synchronous Communication ◽  
Chip Design ◽  
Networks On Chip ◽  
Switch Architecture ◽  
Network Operation ◽  
Placement And Routing ◽  
Delay Variations ◽  
On Chip

In the context of multi-IP chips making use of internal communication paths other than the traditional buses, source synchronous links for use in multi-synchronous Networks-on-Chip (NoCs) are becoming the most vulnerable points for correct network operation and therefore need to be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies, as well as the deterioration due to the ageing of the chip, are the root causes for this. This chapter addresses the challenge of designing a timing variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A timing variation detector senses the misalignment, due to process variation and wearout, between data lines with themselves and with the transmitter clock routed with data in source synchronous links. Then, a suitable delayed replica of the transmitter clock is selected for safe sampling of misaligned data. This chapter proves the robustness of the link in isolation with respect to a detector-less link, also addressing integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.

Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design

2011 ◽  
Vol 2 (4) ◽  
pp. 1-20
Author(s):  
Alessandro Strano ◽  
Carles Hernández ◽  
Federico Silla ◽  
Davide Bertozzi
Keyword(s):  
Cost Effective ◽  
Synchronous Communication ◽  
Chip Design ◽  
Networks On Chip ◽  
Switch Architecture ◽  
Network Operation ◽  
Placement And Routing ◽  
Misaligned Data ◽  
Delay Variations ◽  
On Chip

Source synchronous links for use in multi-synchronous networks-on-chip (NoCs) are becoming the most vulnerable points for correct network operation and must be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies are the root causes for this. This article addresses the challenge of designing a process variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between data lines with themselves and with the transmitter clock routed with data in source synchronous links. A suitable delayed replica of the transmitter clock is then selected for safe sampling of misaligned data. The manuscript proves robustness of the link in isolation with respect to a detector-less link, but also assesses integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.

A Distributed Switch Architecture for On-Chip Networks

2011 ◽  
Author(s):  
Antoni Roca ◽  
Carles Hern´ndez ◽  
Jose Flich ◽  
Federico Silla ◽  
Jose Duato
Keyword(s):  
Switch Architecture ◽  
On Chip

scholarly journals AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation

2019 ◽  
Vol 2019 ◽  
pp. 1-9
Author(s):  
Kizheppatt Vipin
Keyword(s):  
Binary Tree ◽  
Tree Topology ◽  
Clock Frequency ◽  
Traffic Patterns ◽  
Resource Requirement ◽  
Switch Architecture ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip

Binary tree topology generally fails to attract network on chip (NoC) implementations due to its low bisection bandwidth. Fat trees are proposed to alleviate this issue by using increasingly thicker links to connect switches towards the root node. This scheme is very efficient in interconnected networks such as computer networks, which use generic switches for interconnection. In an NoC context, especially for field programmable gate arrays (FPGAs), fat trees require more complex switches as we move higher in the hierarchy. This restricts the maximum clock frequency at which the network operates and offsets the higher bandwidth achieved through using fatter links. In this paper, we discuss the implementation of a binary tree-based NoC, which achieves better bandwidth by varying the clock frequency between the switches as we move higher in the hierarchy. This scheme enables using simpler switch architecture, thus supporting higher maximum frequency of operation. The effect on bandwidth and resource requirement of this architecture is compared with other FPGA-based NoCs for different network sizes and traffic patterns.

Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design

2013 ◽  
pp. 204-221
Author(s):  
Alessandro Strano ◽  
Carles Hernández ◽  
Federico Silla ◽  
Davide Bertozzi
Keyword(s):  
Cost Effective ◽  
Synchronous Communication ◽  
Chip Design ◽  
Networks On Chip ◽  
Switch Architecture ◽  
Network Operation ◽  
Placement And Routing ◽  
Delay Variations ◽  
On Chip

Source synchronous links for use in multi-synchronous networks-on-chip (NoCs) are becoming the most vulnerable points for correct network operation and must be safeguarded against intra-link delay variations and signal misalignments. The intricacy of matching link net attributes during placement and routing and the growing role of process parameter variations in nanoscale silicon technologies are the root causes for this. This article addresses the challenge of designing a process variation and layout mismatch tolerant link for synchronizer-based GALS NoCs by implementing a self-calibration mechanism. A variation detector senses the variability-induced misalignment between data lines with themselves and with the transmitter clock routed with data in source synchronous links. A suitable delayed replica of the transmitter clock is then selected for safe sampling of misaligned data. The manuscript proves robustness of the link in isolation with respect to a detector-less link, but also assesses integration issues with the downstream synchronizer and switch architecture, proving the benefits in a realistic experimental setting for cost-effective NoCs.

Gut microbiome a promising target for management of respiratory diseases

2020 ◽  
Vol 477 (14) ◽  
pp. 2679-2696
Author(s):  
Riddhi Trivedi ◽  
Kalyani Barve
Keyword(s):  
Respiratory Diseases ◽  
New Technology ◽  
Bacterial Flora ◽  
Systemic Circulation ◽  
The Body ◽  
Lung Pathology ◽  
Promising Target ◽  
Current Therapies ◽  
Intestinal Microbial Flora ◽  
On Chip

The intestinal microbial flora has risen to be one of the important etiological factors in the development of diseases like colorectal cancer, obesity, diabetes, inflammatory bowel disease, anxiety and Parkinson's. The emergence of the association between bacterial flora and lungs led to the discovery of the gut–lung axis. Dysbiosis of several species of colonic bacteria such as Firmicutes and Bacteroidetes and transfer of these bacteria from gut to lungs via lymphatic and systemic circulation are associated with several respiratory diseases such as lung cancer, asthma, tuberculosis, cystic fibrosis, etc. Current therapies for dysbiosis include use of probiotics, prebiotics and synbiotics to restore the balance between various species of beneficial bacteria. Various approaches like nanotechnology and microencapsulation have been explored to increase the permeability and viability of probiotics in the body. The need of the day is comprehensive study of mechanisms behind dysbiosis, translocation of microbiota from gut to lung through various channels and new technology for evaluating treatment to correct this dysbiosis which in turn can be used to manage various respiratory diseases. Microfluidics and organ on chip model are emerging technologies that can satisfy these needs. This review gives an overview of colonic commensals in lung pathology and novel systems that help in alleviating symptoms of lung diseases. We have also hypothesized new models to help in understanding bacterial pathways involved in the gut–lung axis as well as act as a futuristic approach in finding treatment of respiratory diseases caused by dysbiosis.

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