An area-efficient VLSI implementation for programmable FIR filters based on a parameterized divide and conquer approach

Thomas Poonnen; Adly T. Fam

doi:10.1016/j.sysarc.2008.05.006

An area-efficient VLSI implementation for programmable FIR filters based on a parameterized divide and conquer approach

Journal of Systems Architecture ◽

10.1016/j.sysarc.2008.05.006 ◽

2008 ◽

Vol 54 (12) ◽

pp. 1122-1128 ◽

Cited By ~ 1

Author(s):

Thomas Poonnen ◽

Adly T. Fam

Keyword(s):

Vlsi Implementation ◽

Divide And Conquer ◽

Fir Filters ◽

Area Efficient

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An area-efficient VLSI implementation for programmable FIR filters based on a parameterized divide and conquer approach

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442) ◽

10.1109/icm.2003.238420 ◽

2003 ◽

Cited By ~ 1

Author(s):

T. Poonnen ◽

A.T. Fam

Keyword(s):

Vlsi Implementation ◽

Divide And Conquer ◽

Fir Filters ◽

Area Efficient

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VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Recent Patents on Computer Science ◽

10.2174/2213275908666150220203501 ◽

2017 ◽

Vol 9 (3) ◽

pp. 216-221

Author(s):

Abdul Kareem ◽

Vardhana M. ◽

Praveen Kumar

Keyword(s):

Low Power ◽

High Speed ◽

Vlsi Implementation ◽

Mathematical Techniques ◽

Area Efficient

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New scan method and pipeline architecture for VLSI implementation of separable 2-D FIR filters without transposition

TENCON 2008 - 2008 IEEE Region 10 Conference ◽

10.1109/tencon.2008.4766758 ◽

2008 ◽

Cited By ~ 2

Author(s):

Basant K. Mohanty ◽

Promod K. Meher

Keyword(s):

Vlsi Implementation ◽

Fir Filters ◽

Pipeline Architecture

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Area Efficient Pipelined VLSI Implementation of List Sphere Decoder

2006 Asia-Pacific Conference on Communications ◽

10.1109/apcc.2006.255901 ◽

2006 ◽

Cited By ~ 3

Author(s):

Jin Lee ◽

Sin-chong Park

Keyword(s):

Vlsi Implementation ◽

Sphere Decoder ◽

Area Efficient

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Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2012.2195062 ◽

2012 ◽

Vol 59 (6) ◽

pp. 371-375 ◽

Cited By ~ 18

Author(s):

Yu-Chi Tsao ◽

Ken Choi

Keyword(s):

Digital Filters ◽

Vlsi Implementation ◽

Linear Phase ◽

Fir Digital Filters ◽

Area Efficient

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Coefficient transformations for area-efficient implementation of multiplier-less FIR filters

Proceedings Eleventh International Conference on VLSI Design ◽

10.1109/icvd.1998.646587 ◽

2002 ◽

Cited By ~ 3

Author(s):

M. Mehendale ◽

S.B. Roy ◽

S.D. Sherlekar ◽

G. Venkatesh

Keyword(s):

Efficient Implementation ◽

Fir Filters ◽

Area Efficient

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VLSI Realization of Area efficient FIR Filters

IOSR Journal of VLSI and Signal processing ◽

10.9790/4200-04421822 ◽

2014 ◽

Vol 4 (4) ◽

pp. 18-22

Author(s):

Neha Bhardwaj ◽

Keyword(s):

Fir Filters ◽

Area Efficient

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VLSI Implementation of Area-Efficient Truncated Modified Booth Multiplier for Signal Processing Applications

Arabian Journal for Science and Engineering ◽

10.1007/s13369-014-1329-7 ◽

2014 ◽

Vol 39 (11) ◽

pp. 7795-7806 ◽

Cited By ~ 1

Author(s):

K. N. Vijeyakumar ◽

V. Sumathy ◽

S. Elango

Keyword(s):

Signal Processing ◽

Vlsi Implementation ◽

Booth Multiplier ◽

Area Efficient

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VLSI Implementation of Area-efficient List Sphere Decoder

2006 International Conference on Communication Technology ◽

10.1109/icct.2006.341862 ◽

2006 ◽

Author(s):

Seungbeom Lee ◽

Jin Lee ◽

Sin-Chong Park

Keyword(s):

Vlsi Implementation ◽

Sphere Decoder ◽

Area Efficient

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VLSI Implementation of Area-Efficient Parallelized Neural Network Accelerator Using Hashing Trick

2019 International SoC Design Conference (ISOCC) ◽

10.1109/isocc47750.2019.9027759 ◽

2019 ◽

Author(s):

Tae Koan Yoo ◽

Jong Kang Park ◽

Jong Tae Kim

Keyword(s):

Neural Network ◽

Vlsi Implementation ◽

Area Efficient

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