A new structure and its analytical model for the electric field and breakdown voltage of SOI high voltage device with variable-k dielectric buried layer

2007 ◽  
Vol 51 (3) ◽  
pp. 493-499 ◽  
Author(s):  
Xiaorong Luo ◽  
Bo Zhang ◽  
Zhaoji Li
Author(s):  
Christoph Jörgens ◽  
Markus Clemens

Purpose In high voltage direct current (HVDC), power cables heat is generated inside the conductor and the insulation during operation. A higher amount of the generated heat in comparison to the dissipated one, results in a possible thermal breakdown. The accumulation of space charges inside the insulation results in an electric field that contributes to the geometric electric field, which comes from the applied voltage. The total electric field decreases in the vicinity of the conductor, while it increases near the sheath, causing a possible change of the breakdown voltage. Design/methodology/approach Here, the thermal breakdown is studied, also incorporating the presence of space charges. For a developed electro-thermal HVDC cable model, at different temperatures, the breakdown voltage is computed through numerical simulations. Findings The simulation results show a dependence of the breakdown voltage on the temperature at the location of the sheath. The results also show only limited influence of the space charges on the breakdown voltage. Research limitations/implications The study is restricted to one-dimensional problems, using radial symmetry of the cable, and does not include any aging or long-term effect of space charges. Such aging effect can locally increase the electric field, resulting in a reduced breakdown voltage. Originality/value A comparison of the breakdown voltage with and without space charges is novel. The chosen approach allows for the first time to assess the influence of space charges and field inversion on the thermal breakdown.


2013 ◽  
Vol 717 ◽  
pp. 158-163
Author(s):  
Phasapon Manosukritkul ◽  
Amonrat Kerdpardist ◽  
Montree Saenlamool ◽  
Ekalak Chaowicharat ◽  
Amporn Poyai ◽  
...  

In this paper, we introduced a P-buried (Pb) layer under trench gate which relieved the electric field crowding in the Non Punch Through Trench gate Insulated Gate Bipolar Transistor (NPT-TIGBT) structure. The Pblayer, with carrier concentration of 5x1016cm-3, was created underneath the trench gate within the n-drift layer. In this way, the concentration of electric field at the trench bottom corner decreased. As a result, the breakdown voltage characteristics of NPT-TIGBT improved. The structures were proposed and verified by T-CAD Sentuarus simulation. From the simulation results, the breakdown voltage increased by approximately 30% compared with conventional NPT-TIGBT.


2007 ◽  
Vol 556-557 ◽  
pp. 1007-1010 ◽  
Author(s):  
Christophe Raynaud ◽  
Daniel Loup ◽  
Phillippe Godignon ◽  
Raul Perez Rodriguez ◽  
Dominique Tournier ◽  
...  

High voltage SiC semiconductor devices have been successfully fabricated and some of them are commercially available [1]. To achieve experimental breakdown voltage values as close as possible to the theoretical value, i.e. value of the theoretical semi-infinite diode, it is necessary to protect the periphery of the devices against premature breakdown due to locally high electric fields. Mesa structures and junction termination extension (JTE) as well as guard rings, and combinations of these techniques, have been successfully employed. Each of them has particular drawbacks. Especially, JTE are difficult to optimize in terms of impurity dose to implant, as well as in terms of geometric dimensions. This paper is a study of the spreading of the electric field at the edge of bipolar diodes protected by JTE and field rings, by optical beam induced current.


2012 ◽  
Vol 21 (7) ◽  
pp. 078502 ◽  
Author(s):  
Xia-Rong Hu ◽  
Bo Zhang ◽  
Xiao-Rong Luo ◽  
Yuan-Gang Wang ◽  
Tian-Fei Lei ◽  
...  

2019 ◽  
pp. 4-14
Author(s):  
V. A. Syasko ◽  
S. S. Golubev ◽  
A. S. Musikhin

The high voltage spark testing method of protective dielectric coatings is applied in almost all manufacture areas and is governed by ISO, ASTM etc. However, all of it doesn’t pay proper attention to high voltage forming (DC or AC) and its polarity relative to electrode, influence of environment and electric field inhomogeneity. In that paper a detailed analysis of air gap breakdown forming processes was given. A dependence of electric field strength on an interelectrode gap length was given for homogeneous and highly inhomogeneous electric fields. It was shown a breakdown voltage of air gaps in highly inhomogeneous field is greatly less than in homogeneous field. Also, it is described the breakdown voltage of air gaps with positive polarity is less then with negative polarity. The possibility coatings testing with a minimum thickness up to 50 m while reducing the testing voltage without reducing the reliability of the results is shown.


2010 ◽  
Vol 19 (3) ◽  
pp. 037303 ◽  
Author(s):  
Hu Sheng-Dong ◽  
Zhang Bo ◽  
Li Zhao-Ji ◽  
Luo Xiao-Rong

2021 ◽  
Author(s):  
Jagamohan Sahoo ◽  
Rajat Mahapatra

Abstract We have developed a simple physics-based two-dimensional analytical Off-state breakdown voltage model of a PBOSS Silicon-On-Insulator Lateral Diffused Metal Oxide Semiconductor (SOI-LDMOS) transistor. The analytical model includes the expressions of surface potential and electric field distributions in the drift region by solving the 2D Poisson’s equation. The electric field at the Si-SiO2 surface is modified by creating additional electric field peaks due to the presence of the PBOSS structure. The uniformly distributed electric field results in improving the breakdown voltage. Further, the breakdown voltage is analytically obtained via critical electric field concept to quantify the breakdown characteristic. The model exploits the impact of the critical device design parameters such as thickness and length of the PBOSS structure, doping, and thickness of the drift region on the surface electric field and the breakdown voltage. The proposed model is verified by the results obtained from ATLAS two dimensional simulations. The analytical model is of the high potential from a physical and mathematical point of view to design high voltage SOI-LDMOS transistors for power switching applications.


Sign in / Sign up

Export Citation Format

Share Document