scholarly journals Area Efficient VLSI Architecture for Square Root Carry Select Adder Using Zero Finding Logic

2016 ◽  
Vol 89 ◽  
pp. 640-650 ◽  
Author(s):  
Bala Sindhuri Kandula ◽  
K. Padma Vasavi ◽  
I. Santi Prabha
Keyword(s):  
Vlsi Architecture ◽  
Square Root ◽  
Carry Select Adder ◽  
Area Efficient

scholarly journals Area and Power Potent VLSI Architecture for Modified CSLA with A Logic Optimization Technique

2019 ◽  
Vol 8 (12) ◽  
pp. 2873-2879 ◽  
Keyword(s):  
Optimization Technique ◽  
Vlsi Architecture ◽  
Performance Constraints ◽  
Area Efficiency ◽  
Logic Optimization ◽  
Ripple Carry Adder ◽  
Overall Performance ◽  
Carry Select Adder ◽  
The Cost ◽  
Area Efficient

Through generations, in an endeavor to pioneer innovative circuit designs, an adder is having the greatest importance as it is a basic building block to decide the system’s overall performance. Wide varieties of adders are used for a plethora of applications in the field of Signal Processing and VLSI systems. Most predominantly used Speed efficient architecture for performing n-bit addition in VLSI applications is Square Root Carry Select Adder (SQRT-CSLA) as it pre-computes the carry and sum by assuming input carry as ‘zero’ and ‘one’. But the overall area usage is high as it uses more number of full adders when compared to Ripple Carry Adder. Though, the existing adder designing techniques are area efficient, there is still scope to achieve area efficiency as area decides the cost of the VLSI Systems. Not only area-efficient but also power potent architectures are required to accelerate the overall performance of the VLSI systems. To meet these objectives, this paper proposes an efficient VLSI architecture for carry select adder by using logic optimization technique addressing performance constraints. The proposed architecture is designed and implemented using cadence encounter tool for different data widths ranging from 16 bits to 128 bits. The performance of the proposed 128-bit architecture achieves an area improvement of 63.43% and a power improvement of 71.00923% when compared to 128-bit SQRT-CSLA architecture

scholarly journals An energy and area efficient yet high-speed square-root carry select adder structure

2017 ◽  
Vol 58 ◽  
pp. 101-112 ◽  
Author(s):  
Milad Bahadori ◽  
Mehdi Kamal ◽  
Ali Afzali-Kusha ◽  
Massoud Pedram
Keyword(s):  
High Speed ◽  
Square Root ◽  
Carry Select Adder ◽  
Area Efficient

scholarly journals An Energy and Area Efficient Carry Select Adder with Dual Carry Adder Cell

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1129
Author(s):  
You ◽  
Yuan ◽  
Tang ◽  
Qiao
Keyword(s):  
Energy Efficient ◽  
Square Root ◽  
Efficient Operation ◽  
Logic Operation ◽  
Simulation Based ◽  
Delay Increase ◽  
Carry Select Adder ◽  
Power Delay Product ◽  
Reduced Power Consumption ◽  
Area Efficient

In this paper, an energy and area efficient carry select adder (CSLA) is proposed. To minimize the redundant logic operation of a regular CSLA, a dual carry adder cell is proposed. The proposed dual carry adder is composed of an XOR/XNOR cell and two pairs of sum-carry cells. Both CMOS logic and a transmission gate were applied to the dual carry adder cell to achieve fast and energy efficient operation. Eight-bit, 16b, and 32b square-root (SQRT) CSLAs based on the proposed dual carry adder were developed. The post-layout simulation based on a SMIC 55 nm process demonstrated that the proposed CSLAs reduced power consumption by 68.4–72.2% with a slight delay increase for different bit widths. As the dual carry adder had much fewer transistors than the two regular full adders, the area of the proposed CSLAs was reduced by 45.8–51.1%. The area-power-delay product of the proposed CSLA improved 5.1×–6.73× compared with the regular CSLA.

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