Subthreshold Circuit Designing and Implementation of Finite Field Multiplier for Cryptography Application

Procedia Computer Science ◽

10.1016/j.procs.2016.03.075 ◽

2016 ◽

Vol 79 ◽

pp. 597-602

Author(s):

Praveen Singh ◽

Vaibhav Neema ◽

Shreeniwas Daulatabad ◽

Ambika Prasad Shah

Keyword(s):

Finite Field ◽

Finite Field Multiplier

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A high speed word level finite field multiplier using reordered normal basis

2008 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2008.4542158 ◽

2008 ◽

Cited By ~ 5

Author(s):

Ashkan Hosseinzadeh Namin ◽

Huapeng Wu ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

High Speed ◽

Normal Basis ◽

Word Level ◽

Finite Field Multiplier

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Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino Logic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2018.2851958 ◽

2018 ◽

Vol 26 (11) ◽

pp. 2542-2552

Author(s):

Parham Hosseinzadeh Namin ◽

Crystal Roma ◽

Roberto Muscedere ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

Normal Basis ◽

Vlsi Implementation ◽

Domino Logic ◽

Finite Field Multiplier

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Speeding up Subquadratic Finite Field Multiplier over GF(2m) Generated by Trinomials Using Toeplitz Matrix-Vector with Inner Product Formula

2011 Fifth International Conference on Genetic and Evolutionary Computing ◽

10.1109/icgec.2011.62 ◽

2011 ◽

Cited By ~ 1

Author(s):

Chiou-Yng Lee ◽

Pramod Kumar Meher

Keyword(s):

Finite Field ◽

Toeplitz Matrix ◽

Product Formula ◽

Inner Product ◽

Finite Field Multiplier ◽

Matrix Vector

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Low power design of a word-level finite field multiplier using Reordered Normal Basis

2015 49th Asilomar Conference on Signals, Systems and Computers ◽

10.1109/acssc.2015.7421165 ◽

2015 ◽

Author(s):

Parham Hosseinzadeh Namin ◽

Roberto Muscedere ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

Low Power ◽

Low Power Design ◽

Normal Basis ◽

Word Level ◽

Finite Field Multiplier

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Efficient VLSI implementation of a finite field multiplier using reordered normal basis

2010 53rd IEEE International Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2010.5548774 ◽

2010 ◽

Cited By ~ 1

Author(s):

Karl Leboeuf ◽

Ashkan Hosseinzadeh Namin ◽

Huapeng Wu ◽

Roberto Muscedere ◽

Majid Ahmadi

Keyword(s):

Finite Field ◽

Normal Basis ◽

Vlsi Implementation ◽

Finite Field Multiplier

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A High-Speed Word Level Finite Field Multiplier in ${\BBF}_{2^m}$ Using Redundant Representation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2008.2003005 ◽

2009 ◽

Vol 17 (10) ◽

pp. 1546-1550 ◽

Cited By ~ 6

Author(s):

A.H. Namin ◽

Huapeng Wu ◽

M. Ahmadi

Keyword(s):

Finite Field ◽

High Speed ◽

Word Level ◽

Finite Field Multiplier ◽

Redundant Representation

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Design of Fast Finite Field Multiplier based on Noramal Basis

Indian Journal of Science and Technology ◽

10.17485/ijst/2015/v8i34/86663 ◽

2015 ◽

Vol 8 (34) ◽

Author(s):

Jae Yeon Choi

Keyword(s):

Finite Field ◽

Finite Field Multiplier

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Low-complexity systolic design for finite field multiplier

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE) ◽

10.1109/icgccee.2014.6922224 ◽

2014 ◽

Cited By ~ 1

Author(s):

T. P. Rajalakshmi ◽

C. B. Rajesh

Keyword(s):

Finite Field ◽

Low Complexity ◽

Finite Field Multiplier

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Design of reconfigurable general finite field multiplier in GF[2/sup m/]

The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004. ◽

10.1109/newcas.2004.1359100 ◽

2004 ◽

Cited By ~ 1

Author(s):

Hua Li

Keyword(s):

Finite Field ◽

Finite Field Multiplier

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Bit-parallel finite field multiplier and squarer using polynomial basis

IEEE Transactions on Computers ◽

10.1109/tc.2002.1017695 ◽

2002 ◽

Vol 51 (7) ◽

pp. 750-758 ◽

Cited By ~ 106

Author(s):

Huapeng Wu

Keyword(s):

Finite Field ◽

Polynomial Basis ◽

Finite Field Multiplier

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