Study of cascaded tunable DFB semiconductor laser with wide tuning range and high single mode yield based on equivalent phase shift technique

2015 ◽  
Vol 352 ◽  
pp. 70-76 ◽  
Author(s):  
Lianyan Li ◽  
Song Tang ◽  
Jun Lu ◽  
Yuechun Shi ◽  
Baoli Cao ◽  
...  
Keyword(s):  
Phase Shift ◽  
Semiconductor Laser ◽  
Tuning Range ◽  
Single Mode ◽  
Wide Tuning Range ◽  
Shift Technique ◽  
Dfb Semiconductor Laser

1.3 W Single-Frequency Tapered Semiconductor Laser Amplification System with Wide Tuning Range

2018 ◽  
Vol 55 (12) ◽  
pp. 121401
Author(s):  
李钱 Li Qian ◽  
万敏 Wan Min ◽  
鲁燕华 Lu Yanhua ◽  
许夏飞 Xu Xiafei ◽  
任怀瑾 Ren Huaijin ◽  
...  
Keyword(s):  
Semiconductor Laser ◽  
Tuning Range ◽  
Single Frequency ◽  
Wide Tuning Range ◽  
Laser Amplification ◽  
Amplification System

scholarly journals Improved Single-Mode Property of DFB Semiconductor Laser Based on Sampling Technique Using Chirp Compensation

2015 ◽  
Vol 7 (1) ◽  
pp. 1-10 ◽  
Author(s):  
Yuechun Shi ◽  
Jilin Zheng ◽  
Naizhuo Jiang ◽  
Lianyan Li ◽  
Yunshan Zhang ◽  
...  
Keyword(s):  
Semiconductor Laser ◽  
Sampling Technique ◽  
Single Mode ◽  
Chirp Compensation ◽  
Dfb Semiconductor Laser

Miniature packaged external-cavity semiconductor laser with 50 GHz continuous electrical tuning range

1988 ◽  
Vol 24 (16) ◽  
pp. 988 ◽  
Author(s):  
J. Mellis ◽  
S.A. Al-Chalabi ◽  
K.H. Cameron ◽  
R. Wyatt ◽  
J.C. Regnault ◽  
...  
Keyword(s):  
Semiconductor Laser ◽  
Tuning Range ◽  
External Cavity

scholarly journals A Novel Fast-Locking ADPLL Based on Bisection Method

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1382
Author(s):  
Xiaoying Deng ◽  
Huazhang Li ◽  
Mingcheng Zhu
Keyword(s):  
High Performance ◽  
Tuning Range ◽  
Frequency Control ◽  
Control Word ◽  
Cmos Process ◽  
Bisection Method ◽  
Reference Frequency ◽  
Wide Tuning Range ◽  
Cascade Structure ◽  
And Control

Based on the idea of bisection method, a new structure of All-Digital Phased-Locked Loop (ADPLL) with fast-locking is proposed. The structure and locking method are different from the traditional ADPLLs. The Control Circuit consists of frequency compare module, mode-adjust module and control module, which is responsible for adjusting the frequency control word of digital-controlled-oscillator (DCO) by Bisection method according to the result of the frequency compare between reference clock and restructure clock. With a high frequency cascade structure, the DCO achieves wide tuning range and high resolution. The proposed ADPLL was designed in SMIC 180 nm CMOS process. The measured results show a lock range of 640-to-1920 MHz with a 40 MHz reference frequency. The ADPLL core occupies 0.04 mm2, and the power consumption is 29.48 mW, with a 1.8 V supply. The longest locking time is 23 reference cycles, 575 ns, at 1.92 GHz. When the ADPLL operates at 1.28 GHz–1.6 GHz, the locking time is the shortest, only 9 reference cycles, 225 ns. Compared with the recent high-performance ADPLLs, our design shows advantages of small area, short locking time, and wide tuning range.

Sign in / Sign up

Export Citation Format

Share Document