A fusion prognostics-based qualification test methodology for microelectronic products

2016 ◽  
Vol 63 ◽  
pp. 320-324 ◽  
Author(s):  
Michael Pecht ◽  
Tadahiro Shibutani ◽  
Myeongsu Kang ◽  
Melinda Hodkiewicz ◽  
Edward Cripps
Keyword(s):  
Qualification Test ◽  
Test Methodology ◽  
Fusion Prognostics

Defect Snap Shot: Quick Isolation and Mapping of Interconnect Defects for Backend Yield Improvement

2004 ◽  
Author(s):  
Jenny Fan ◽  
Dave Mark
Keyword(s):  
Metal Layer ◽  
Single Layer ◽  
Yield Improvement ◽  
Test Methodology ◽  
Process Complexity

Abstract Metal interconnect defects have become a more serious yield detractor as backend process complexity has increased from a single layer to about 10 layers. This paper introduces a test methodology to monitor and localize the metal defects based on FPGA products. The test patterns are generated for each metal layer. The results not only indicate the severity of defects for each metal layer, but also accurately isolate open/short defects.

Evaluation of the Resistance of Individual Si Die to Cracking

1998 ◽  
Author(s):  
R. Berriche ◽  
R.K. Lowry ◽  
M.I. Rosenfield
Keyword(s):  
Thermal Cycling ◽  
Hardness Test ◽  
Mechanical Stresses ◽  
Test Method ◽  
Processing Conditions ◽  
Micro Hardness ◽  
Test Methodology ◽  
Vickers Micro Hardness

Abstract The present work investigated the use of the Vickers micro-hardness test method to determine the resistance of individual die to cracking. The results are used as an indicator of resistance to failure under the thermal and mechanical stresses of packaging and subsequent thermal cycling. Indentation measurements on die back surfaces are used to determine how changes in wafer backside processing conditions affect cracks that form around impressions produced at different loads. Test methodology and results obtained at different processing conditions are discussed.

Improving Yield Using Scan and DFT Based Analysis for High Performance PowerPC© Microprocessor

2006 ◽  
Author(s):  
Ray Talacka ◽  
Nandu Tendolkar ◽  
Cynthia Paquette
Keyword(s):  
High Performance ◽  
Yield Enhancement ◽  
Test Time ◽  
Balance Test ◽  
Specific Test ◽  
Defect Location ◽  
Test Methodology ◽  
Memory Arrays ◽  
Scan Chain ◽  
Scan Pattern

Abstract The use of memory arrays to drive yield enhancement has driven the development of many technologies. The uniformity of the arrays allows for easy testing and defect location. Unfortunately, the complexities of the logic circuitry are not represented well in the memory arrays. As technologies push to smaller geometries and the layout and timing of the logic circuitry become more problematic the ability to address yield issue is becoming critical. This paper presents the added yield enhancement capabilities of using e600 core Scan Chain and Scan Pattern testing for logic debug, ways to interpret the fail data, and test methodologies to balance test time and acquiring data. Selecting a specific test methodology and using today's advanced tools like Freescale's DFT/FA has been proven to find more yield issues, earlier, enabling quicker issue resolution.

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