Interfacial reaction and failure mode analysis of the solder joints for flip-chip LED on ENIG and Cu-OSP surface finishes

2015 ◽  
Vol 55 (8) ◽  
pp. 1234-1240 ◽  
Author(s):  
Yang Liu ◽  
Fenglian Sun ◽  
Hao Zhang ◽  
Tong Xin ◽  
Cadmus A. Yuan ◽  
...  
Keyword(s):  
Failure Mode ◽  
Interfacial Reaction ◽  
Flip Chip ◽  
Solder Joints ◽  
Mode Analysis ◽  
Surface Finishes ◽  
Failure Mode Analysis

Failure mode analysis of lead-free solder joints under high speed impact testing

2008 ◽  
Vol 494 (1-2) ◽  
pp. 196-202 ◽  
Author(s):  
De-Shin Liu ◽  
Chia-Yuan Kuo ◽  
Chang-Lin Hsu ◽  
Geng-Shin Shen ◽  
Yu-Ren Chen ◽  
...  
Keyword(s):  
Failure Mode ◽  
High Speed ◽  
Solder Joints ◽  
Impact Testing ◽  
Lead Free ◽  
Mode Analysis ◽  
Lead Free Solder ◽  
High Speed Impact ◽  
Failure Mode Analysis ◽  
Free Solder

Case Study and Fault Modeling for Wrong Redundancy Evaluation on DRAM Devices

2007 ◽  
Author(s):  
Martin Versen ◽  
Dorina Diaconescu ◽  
Jerome Touzel
Keyword(s):  
Failure Mode ◽  
Failure Modes ◽  
Fault Modeling ◽  
Mode Analysis ◽  
Root Cause ◽  
Failure Mode Analysis

Abstract The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.

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