Process variation aware dual-Vth assignment technique for low power nanoscale CMOS design
2011 ◽
Vol 51
(12)
◽
pp. 2357-2365
◽
2015 ◽
Vol E98.C
(12)
◽
pp. 1091-1104
◽
2008 ◽
Vol 55
(6)
◽
pp. 606-606
2007 ◽
pp. 13-39
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