Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact

2008 ◽  
Vol 48 (8-9) ◽  
pp. 1149-1154 ◽  
Author(s):  
Chan-Yen Chou ◽  
Tuan-Yu Hung ◽  
Shin-Yueh Yang ◽  
Ming-Chih Yew ◽  
Wen-Kun Yang ◽  
...  
Keyword(s):  
Solder Joint ◽  
Experimental Validation ◽  
Drop Impact ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Failure Simulation ◽  
Trace Line

Micro to Macro Thermo-Mechanical Simulation of Wafer Level Packaging

2003 ◽  
Vol 125 (4) ◽  
pp. 576-581 ◽  
Author(s):  
Chang-An Yuan ◽  
Kou-Ning Chiang
Keyword(s):  
Solder Joint ◽  
Three Dimensional ◽  
Element Model ◽  
Computer Hardware ◽  
Beam Model ◽  
Wafer Level ◽  
Scaled Model ◽  
Cpu Time ◽  
Wafer Level Packaging ◽  
Constraint Method

Due to the CPU limitation of the computer hardware currently available, the three-dimensional full-scaled finite element model of wafer level packaging is impractical for the reliability analysis and fatigue life prediction. In order to significantly reduce the simulation CPU time, an equivalent beam method based on the micro-macro technique with multi-point constraint method is proposed in the present study. The proposed novel equivalent beam consists of three/five sections to simulate the three-dimensional solder joint with different upper/lower pad size. Moreover, the total length of the proposed equivalent beam equals to the stand-of-height of the realistic solder joint. To compare the results of equivalent beam and full-scaled model, a wafer level packaging with 48 I/O is selected as a benchmark model in this study. The result shows that the equivalent beam model can reduce approximately 80 percent CPU time, and good agreement between the equivalent beam model and the full-scaled model are achieved.

Investigation of the Trace Line Failure Mechanism and Design of Flexible Wafer Level Packaging

2009 ◽  
Vol 32 (2) ◽  
pp. 390-398 ◽  
Author(s):  
Ming-Chih Yew ◽  
C.C.A. Yuan ◽  
Chung-Jung Wu ◽  
Dyi-Chung Hu ◽  
Wen-Kun Yang ◽  
...  
Keyword(s):  
Failure Mechanism ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Trace Line

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

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