Material properties of anisotropic conductive films (ACFs) and their flip chip assembly reliability in NAND flash memory applications

2008 ◽  
Vol 48 (7) ◽  
pp. 1052-1061 ◽  
Author(s):  
Kyung-Woon Jang ◽  
Chang-Kyu Chung ◽  
Woong-Sun Lee ◽  
Kyung-Wook Paik
Keyword(s):  
Material Properties ◽  
Flash Memory ◽  
Flip Chip ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Conductive Films ◽  
Flip Chip Assembly ◽  
Memory Applications

The Influence of Nitrogen Doping on the Chemical and Local Bonding Environment of Amorphous and Crystalline Ge2Sb2Te5

2009 ◽  
Vol 1160 ◽  
Author(s):  
Joseph Washington ◽  
Eric A. Joseph ◽  
Michael A. Paesler ◽  
Gerald Lucovsky ◽  
Jean L. Jordan-Sweet ◽  
...  
Keyword(s):  
Grain Boundary ◽  
Flash Memory ◽  
Nitrogen Doping ◽  
Phase Change Materials ◽  
Annealed Film ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Local Bonding ◽  
Memory Applications

AbstractRecent interest in phase change materials (PCMs) for non-volatile memory applications has been fueled by the promise of scalability beyond the limit of conventional DRAM and NAND flash memory [1]. However, for such solid state device applications, Ge2Sb2Te5 (GST), GeSb, and other chalcogenide PCMs require doping. Doping favorably modifies crystallization speed, crystallization temperature, and thermal stability but the chemical role of the dopant is not yet fully understood. In this work, X-ray Absorption Fine Spectroscopy (XAFS) is used to examine the chemical and structural role of nitrogen doping (N-) in as-deposited and crystalline GST thin films. The study focuses on the chemical and local bonding environment around each of the elements in the sample, in pre and post-anneal states, and at various doping concentrations. We conclude that the nitrogen dopant forms stable Ge-N bonds as deposited, which is distinct from GST bonds, and remain at the grain boundary of the crystallites such that the annealed film is comprised of crystallites with a dopant rich grain boundary.

Field-dependent charge trapping analysis of ONO inter-poly dielectrics for NAND flash memory applications

2014 ◽  
Vol 94 ◽  
pp. 51-55 ◽  
Author(s):  
Pyung Moon ◽  
Jun Yeong Lim ◽  
Tae-Un Youn ◽  
Sung-Kye Park ◽  
Ilgu Yun
Keyword(s):  
Flash Memory ◽  
Charge Trapping ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Field Dependent ◽  
Memory Applications

Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer)

2012 ◽  
Vol E95.C (5) ◽  
pp. 837-841 ◽  
Author(s):  
Se Hwan PARK ◽  
Yoon KIM ◽  
Wandong KIM ◽  
Joo Yun SEO ◽  
Hyungjin KIM ◽  
...  
Keyword(s):  
Flash Memory ◽  
Three Dimensional ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Memory Array

scholarly journals Artificial Neural Network Assisted Error Correction for MLC NAND Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 879
Author(s):  
Ruiquan He ◽  
Haihua Hu ◽  
Chunru Xiong ◽  
Guojun Han
Keyword(s):  
Neural Network ◽  
Error Correction ◽  
Error Detection ◽  
Flash Memory ◽  
Nand Flash ◽  
Data Reliability ◽  
Nand Flash Memory ◽  
Process Technology ◽  
Noise Mitigation ◽  
Memory Channel

The multilevel per cell technology and continued scaling down process technology significantly improves the storage density of NAND flash memory but also brings about a challenge in that data reliability degrades due to the serious noise. To ensure the data reliability, many noise mitigation technologies have been proposed. However, they only mitigate one of the noises of the NAND flash memory channel. In this paper, we consider all the main noises and present a novel neural network-assisted error correction (ANNAEC) scheme to increase the reliability of multi-level cell (MLC) NAND flash memory. To avoid using retention time as an input parameter of the neural network, we propose a relative log-likelihood ratio (LLR) to estimate the actual LLR. Then, we transform the bit detection into a clustering problem and propose to employ a neural network to learn the error characteristics of the NAND flash memory channel. Therefore, the trained neural network has optimized performances of bit error detection. Simulation results show that our proposed scheme can significantly improve the performance of the bit error detection and increase the endurance of NAND flash memory.

scholarly journals Investigation of Re-program Scheme in Charge Trap Based 3D NAND Flash Memory

2021 ◽  
pp. 1-1
Author(s):  
Ting Cheng ◽  
Jianquan Jia ◽  
Lei Jin ◽  
Xinlei Jia ◽  
Shiyu Xia ◽  
...  
Keyword(s):  
Flash Memory ◽  
Program Scheme ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Charge Trap
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