A CAD approach for pre-layout optimal PDN design and its post-layout verification

2019 ◽  
Vol 65 ◽  
pp. 158-168 ◽  
Author(s):  
Moumita Chakraborty ◽  
Debasri Saha ◽  
Amlan Chakrabarti ◽  
Sayani Bindai
Keyword(s):  
Layout Verification

A study of advanced layout verification to prevent leakage current failure during power down mode operation

2002 ◽  
Vol 42 (9-11) ◽  
pp. 1385-1388 ◽  
Author(s):  
Yong-Ha Songa ◽  
Myoung-Lae Parkb ◽  
Gye-Won Junga ◽  
Taek-Soo Kima
Keyword(s):  
Leakage Current ◽  
Mode Operation ◽  
Layout Verification

ViTaL: Verifying Trojan-Free Physical Layouts through Hardware Reverse Engineering

2021 ◽  
Author(s):  
Matthias Ludwig ◽  
Ann-Christin Bette ◽  
Bernhard Lippmann
Keyword(s):  
Integrated Circuits ◽  
Reverse Engineering ◽  
Semiconductor Industry ◽  
Statistical Validation ◽  
User Input ◽  
Detection Techniques ◽  
Fine Pitch ◽  
Layout Verification ◽  
First Time ◽  
Physical Layout

The semiconductor industry is heavily relying on outsourcing of design, fabrication, and testing to third parties. The threat of possibly malicious actors in this ramified supply-chain poses a risk for the integrity of integrated circuits (ICs) and hardware Trojans (HTs) are a heavily discussed topic in academia and the industry. A variety of pre- and post-silicon HT prevention and detection techniques has been suggested in prior works. Hardware reverse engineering has the potential to detect potential modification in physical layouts. Yet, there is no model to qualitatively and quantitatively rate the complex and expensive reverse engineering (RE) process addressing its inherent process aberrations and consequently provide a tool for layout verification. The ViTaL framework introduces a statistical validation technique, based on physical layout verification through RE and considers all potential sources of errors. The golden-model based framework is technology-agnostic, scaleable, and user input is optional. For the first time, results of fine pitch metallization layers of a CMOS 40nm process node IC are presented quantitatively and the limitations and possibilities are discussed.<br>

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