A low power multi-rate decoder hardware for IEEE 802.11n LDPC codes

2012 ◽  
Vol 36 (3) ◽  
pp. 159-166 ◽  
Author(s):  
Merve Peyic ◽  
Hakan Baba ◽  
Erdem Guleyuboglu ◽  
Ilker Hamzaoglu ◽  
Mehmet Keskinoz
Keyword(s):  
Low Power ◽  
Ldpc Codes ◽  
Ieee 802.11N

Performance of IEEE 802.11n LDPC codes

2017 ◽  
Vol 11 (22) ◽  
pp. 1065-1073
Author(s):  
Yenny Alexandra Avendano Martinez ◽  
Octavio Jose Salcedo Parra ◽  
Giovanny Mauricio Tarazona Bermudez
Keyword(s):  
Error Detection ◽  
High Performance ◽  
Ldpc Codes ◽  
Low Density ◽  
Parity Check ◽  
Ieee 802.11N ◽  
Noise Environment ◽  
Low Density Parity Check ◽  
Parity Check Codes

LDPC (Low Density Parity Check Codes) is a set of algorithms that send, receive and correct in a noise environment, frames transmitted in a LAN environment. This article demonstrates the high performance of the LDPC in environments of noise, compared to the CRC error detection code highly currently implemented, in this way the efficiency of LDPC is shown specifically over the 802. 11n protocol.

scholarly journals A Hybrid Statistical and Prioritised Unequal Error Protection Scheme for IEEE 802.11n LDPC Codes

2017 ◽  
Vol 8 (1) ◽  
pp. 1-9 ◽  
Author(s):  
Tulsi Pawan Fowdur ◽  
Madhavsingh Indoonundon
Keyword(s):  
Ldpc Codes ◽  
Ldpc Code ◽  
Error Correcting Codes ◽  
Code Word ◽  
Unequal Error Protection ◽  
Node Degree ◽  
Error Protection ◽  
Ieee 802.11N ◽  
Protection Scheme ◽  
Power Region

The combination of powerful error correcting codes such as (LDPC) codes and Quadrature Amplitude Modulation (QAM) has been widely deployed in wireless communication standards such as the IEEE 802.11n and DVB-T2. Recently, several Unequal Error Protection schemes which exploit non-uniform degree distribution of bit nodes in irregular LDPC codes have been proposed. In parallel, schemes that exploit the inherent UEP characteristics of the QAM constellation have also been developed. In this paper, a hybrid UEP scheme is proposed for LDPC codes with QAM. The scheme uses statistical distribution of source symbols to map the systematic bits of the LDPC encoded symbols to the QAM constellation. Essentially, systematic symbols having highest probabilities of occurrence are mapped onto the low power region of the QAM constellation and those with a low probability of occurrence are mapped onto the high power region. The decrease in overall transmission power allows for an increased spacing between the QAM constellation points. Additionally, the scheme uses the distribution of the bit node degree of the LDPC code-word to map the parity bits having the highest degree onto prioritised QAM constellation points. Simulations with the IEEE 802.11n LDPC codes revealed that the proposed scheme can provide gains of up to 0.91 dB in Eb/No compared with other UEP schemes for a range of Bit Error Rate (BER) values

scholarly journals Low Power Decoding of LDPC Codes

2013 ◽  
Vol 2013 ◽  
pp. 1-12 ◽  
Author(s):  
Mohamed Ismail ◽  
Imran Ahmed ◽  
Justin Coon
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Low Power ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Efficient Solutions ◽  
Design Flow ◽  
Wireless Sensor ◽  
Battery Life ◽  
Ldpc Decoding

Wireless sensor networks are used in many diverse application scenarios that require the network designer to trade off different factors. Two such factors of importance in many wireless sensor networks are communication reliability and battery life. This paper describes an efficient, low complexity, high throughput channel decoder suited to decoding low-density parity-check (LDPC) codes. LDPC codes have demonstrated excellent error-correcting ability such that a number of recent wireless standards have opted for their inclusion. Hardware realisation of practical LDPC decoders is a challenging area especially when power efficient solutions are needed. Implementation details are given for an LDPC decoding algorithm, termed adaptive threshold bit flipping (ATBF), designed for low complexity and low power operation. The ATBF decoder was implemented in 90 nm CMOS at 0.9 V using a standard cell design flow and was shown to operate at 250 MHz achieving a throughput of 252 Gb/s/iteration. The decoder area was 0.72 mm2 with a power consumption of 33.14 mW and a very small energy/decoded bit figure of 1.3 pJ.

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