Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects

2011 ◽  
Vol 35 (6) ◽  
pp. 579-592 ◽  
Author(s):  
S. Saponara ◽  
L. Fanucci ◽  
M. Coppola
Keyword(s):  
Network On Chip ◽  
Network Interface ◽  
On Chip

Design and verification of an efficient WISHBONE-based network interface for network on chip

2014 ◽  
Vol 40 (6) ◽  
pp. 1838-1857 ◽  
Author(s):  
K. Swaminathan ◽  
G. Lakshminarayanan ◽  
Seok-Bum Ko
Keyword(s):  
Network On Chip ◽  
Network Interface ◽  
On Chip

Design and implementation of low latency network interface for network on chip

2010 ◽  
Author(s):  
Brahim Attia ◽  
Wissem Chouchene ◽  
Abdelkrim Zitouni ◽  
Abid Nourdin ◽  
Rached Tourki
Keyword(s):  
Network On Chip ◽  
Network Interface ◽  
Low Latency ◽  
Design And Implementation ◽  
On Chip

High Speed Low Power Ping Pong Buffering Based Network Interface for Network on Chip

2013 ◽  
Vol 9 (3) ◽  
pp. 322-331 ◽  
Author(s):  
K. Swaminathan ◽  
G. Lakshminarayanan ◽  
Seok-Bum Ko
Keyword(s):  
Low Power ◽  
High Speed ◽  
Network On Chip ◽  
Network Interface ◽  
Ping Pong ◽  
On Chip

Keys for Administration of Reconfigurable NoC

2010 ◽  
pp. 67-83
Author(s):  
Rachid Dafali ◽  
Jean-Philippe Diguet
Keyword(s):  
Dynamic Reconfiguration ◽  
Network On Chip ◽  
Network Protocol ◽  
Current Work ◽  
Network Interface ◽  
Adaptive Network ◽  
Research Issues ◽  
Network Layers ◽  
On Chip ◽  
Open Issues

This chapter presents an analysis of current needs in the domain of Reconfigurable Network on chip. We first detail our motivations for NoC reconfiguration, which is followed by a description of our model for Reconfigurable Network on chip in relation with the usual OSI network layers. Then, we propose a study of outstanding research issues of current work and open issues organized into three topics: dynamic reconfiguration administration, network infrastructure reconfiguration and network protocol reconfiguration. To finish, we present our strategy for reconfiguration and introduce a self-adaptive Network Interface architecture as a part of the configuration manager.

A new pipelined network interface for Network on Chip with latency and jitter optimization

2011 ◽  
Author(s):  
Brahim Attia ◽  
Chouchene Wissem ◽  
Abid Noureddine ◽  
Abdelkrim Zitouni ◽  
Kholdoun Torki ◽  
...  
Keyword(s):  
Network On Chip ◽  
Network Interface ◽  
On Chip

PERFORMANCE IMPACT OF TASK-TO-TASK COMMUNICATION PROTOCOL IN NETWORK-ON-CHIP

2009 ◽  
Vol 18 (02) ◽  
pp. 283-294 ◽  
Author(s):  
NADER BAGHERZADEH ◽  
MASARU MATSUURA
Keyword(s):  
Communication Protocol ◽  
Network On Chip ◽  
Network Interface ◽  
Task Structure ◽  
Performance Impact ◽  
Trade Offs ◽  
Basic Protocol ◽  
Interconnect Design ◽  
Strong Candidate ◽  
On Chip

Network-on-Chip (NoC) is a strong candidate for scalable interconnect design of Multi-Processor System-on-Chip (MPSoC). Software tasks of MPSoC require a certain protocol to communicate with each other. In NoC such a communication protocol should be handled at Network Interface and/or Processor Element level and it is expected that different protocols show their trade-offs. In consideration of the above, we employed two types of basic protocol and investigated their performance impact. The contribution of this work is to quantitatively evaluate effectiveness of using separate communication protocols depending on the task structure.

Sign in / Sign up

Export Citation Format

Share Document