Ground plane fin-shaped field effect transistor (GP-FinFET): A FinFET for low leakage power circuits

2012 ◽  
Vol 95 ◽  
pp. 74-82 ◽  
Author(s):  
Mehdi Saremi ◽  
Ali Afzali-Kusha ◽  
Saeed Mohammadi
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Ground Plane ◽  
Leakage Power ◽  
Low Leakage ◽  
Effect Transistor ◽  
Power Circuits

scholarly journals Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing

2021 ◽  
Author(s):  
Garima Jain ◽  
Ravinder Singh Sawhney ◽  
Ravinder Kumar ◽  
Amit Saini
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Subthreshold Swing ◽  
Short Channel ◽  
Tunneling Mechanism ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Abstract In this paper, a novel vertically stacked silicon Nanosheet Tunnel Field Effect Transistor (NS-TFET) device scaled to a gate length of 12nm with Contact poly pitch (CPP) of 48nm is simulated. NS-TFET device is investigated for its electrostatics characteristics using technology computer-aided design (TCAD) simulator. The inter-band tunneling mechanism with a P-I-N layout has been incorporated in the stacked nanosheet devices. The asymmetric design technique for doping has been used for optimum results. NS-TFET provides a low leakage current of order10-16 A, an excellent subthreshold swing (SW) of 23mv/decade, and negligible drain induced barrier lowering (DIBL) having a value of 10.5 mv/V. The notable ON to OFF current ratio of the order of 1011 has been achieved. The device exhibits a high transconductance of 3.022x10-5 S at the gate to source voltage of 1V. NS-TFET shows tremendous improvement in short channel effects (SCE) and is a good option for advanced technologies.

Low-Leakage-Current Enhancement-Mode AlGaN/GaN Heterostructure Field-Effect Transistor Using p-Type Gate Contact

2006 ◽  
Vol 45 (No. 11) ◽  
pp. L319-L321 ◽  
Author(s):  
Norio Tsuyukuchi ◽  
Kentaro Nagamatsu ◽  
Yoshikazu Hirose ◽  
Motoaki Iwaya ◽  
Satoshi Kamiyama ◽  
...  
Keyword(s):  
Leakage Current ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Enhancement Mode ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Effect Transistor ◽  
Gan Heterostructure ◽  
P Type

Boosting on Current Using Various Source Material for Dual Gate Tunnel Field Effect Transistor

2021 ◽  
Vol 7 (1) ◽  
Author(s):  
Priyadarshini N D ◽  
Nayana G H ◽  
P Vimala
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Source Material ◽  
Oxide Semiconductor ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Dual Gate ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor

Tunnel Field Effect Transistors (TFET) have demonstrated to have likely applications in the cutting-edge low force and super low force semiconductors to substitute the conventional FETs. TFET will be able to provide steep inverse subthreshold swing slope also maintaining a low leakage current, making it an essential structure for limiting the power consumption in Metal Oxide Semiconductor FETs.In this paper, we are simulating different structures of TFET by varying source material to boost the ON current of the device. The different models are designed and simulated using Silvaco TCAD simulator and transfer characteristics are studied.

Leakage reduction technique for nano-scaled devices

Circuit World ◽  
2020 ◽  
Vol 47 (1) ◽  
pp. 97-104 ◽  
Author(s):  
Shilpi Birla ◽  
Sudip Mahanti ◽  
Neha Singh
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Average Power ◽  
Cmos Technology ◽  
Power Reduction ◽  
Leakage Power ◽  
Content Type ◽  
Leakage Reduction ◽  
Reduction Techniques ◽  
Effect Transistor

Purpose The purpose of this paper is to propose a leakage reduction technique which will works for complementary metal oxide semiconductor (CMOS) and fin field effect transistor (FinFET). Power consumption will always remain one of the major concerns for the integrated circuit (IC) designers. Presently, leakage power dominates the total power consumption, which is a severe issue. It is undoubtedly clear that the scaling of CMOS revolutionizes the IC industry. Still, on the contrary, scaling of the size of the transistor has raised leakage power as one of the significant threats to the IC industry. Scaling of the devices leads to the scaling of other device parameters, which includes threshold voltage also. The scaling of threshold voltage leads to an exponential increase in the sub-threshold current. So, many leakage reduction techniques have been proposed by researchers for CMOS from time to time. Even the other nano-scaled devices such as FinFET, carbon nanotube field effect transistor and tunneling field effect transistor, have been introduced, and FinFET is the one which has evolved as the most favorable candidate for replacing CMOS technology. Design/methodology/approach Because of its minimum leakage and without having limitation of the short channel effects, it gradually started replacing the CMOS. In this paper, the authors have proposed a technique for leakage reduction for circuits using nano-scaled devices such as CMOS and FinFET. They have compared the proposed PMOS FOOTER SLEEP with the existing leakage reduction techniques such as LECTOR technique, LECTOR FOOTER SLEEP technique. The proposed technique has been implemented using CMOS and FinFET devices. This study found that the proposed method reduces the average power, as well as leakage power reduction, for both CMOS and FinFET devices. Findings This study found that the proposed method reduces the average power as well as leakage power reduction for both CMOS and FinFET devices. The delay has been calculated for the proposed technique and the existing techniques, which verifies that the proposed technique is suitable for high-speed circuit applications. The authors have implemented higher order gates to verify the performance of the proposed circuit. The proposed method is suitable for deep-submicron CMOS technology and FinFET technology. Originality/value All the existing techniques were proposed for either CMOS device or FinFET device, but the authors have implemented all the techniques with both the devices and verified with the proposed technique for CMOS as well as FinFET devices.

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