scholarly journals Fault detection and a differential fault analysis countermeasure for the Montgomery power ladder in elliptic curve cryptography

2012 ◽  
Vol 55 (1-2) ◽  
pp. 256-267 ◽  
Author(s):  
Ihor Vasyltsov ◽  
Gokay Saldamli
Keyword(s):  
Fault Detection ◽  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
Fault Analysis ◽  
Differential Fault Analysis

A Hybrid Countermeasure-Based Fault-Resistant AES Implementation

2019 ◽  
Vol 29 (03) ◽  
pp. 2050044
Author(s):  
Noura Benhadjyoussef ◽  
Mouna Karmani ◽  
Mohsen Machhout ◽  
Belgacem Hamdi
Keyword(s):  
Fault Detection ◽  
Fault Analysis ◽  
Advanced Encryption Standard ◽  
Implementation Cost ◽  
Additional Time ◽  
Area Overhead ◽  
Differential Fault Analysis ◽  
Detection Capabilities ◽  
Xilinx Fpga ◽  
Detection Schemes

A Fault-Resistant scheme has been proposed to secure the Advanced Encryption Standard (AES) against Differential Fault Analysis (DFA) attack. In this paper, a hybrid countermeasure has been presented in order to protect a 32-bits AES architecture proposed for resource-constrained embedded systems. A comparative study between the most well-known fault detection schemes in terms of fault detection capabilities and implementation cost has been proposed. Based on this study, we propose a hybrid fault resistant scheme to secure the AES using the parity detection for linear operations and the time redundancy for SubBytes operation. The proposed scheme is implemented on the Virtex-5 Xilinx FPGA board in order to evaluate the efficiency of the proposed fault-resistant scheme in terms of area, time costs and fault coverage (FC). Experimental results prove that the countermeasure achieves a FC with about 98,82% of the injected faults detected during the 32-bits AES process. The area overhead of the proposed countermeasure is about 14% and the additional time delay is about 13%.

scholarly journals Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES

Sensors ◽  
2021 ◽  
Vol 21 (16) ◽  
pp. 5655
Author(s):  
Ignacio Algredo-Badillo ◽  
Kelsey A. Ramírez-Gutiérrez ◽  
Luis Alberto Morales-Rosales ◽  
Daniel Pacheco Bautista ◽  
Claudia Feregrino-Uribe
Keyword(s):  
Fault Detection ◽  
Error Detection ◽  
Secure Communication ◽  
Critical Path ◽  
Fault Analysis ◽  
Hardware Architecture ◽  
Secret Key ◽  
Cryptographic Algorithm ◽  
Differential Fault Analysis ◽  
Error Detection And Correction

Currently, cryptographic algorithms are widely applied to communications systems to guarantee data security. For instance, in an emerging automotive environment where connectivity is a core part of autonomous and connected cars, it is essential to guarantee secure communications both inside and outside the vehicle. The AES algorithm has been widely applied to protect communications in onboard networks and outside the vehicle. Hardware implementations use techniques such as iterative, parallel, unrolled, and pipeline architectures. Nevertheless, the use of AES does not guarantee secure communication, because previous works have proved that implementations of secret key cryptosystems, such as AES, in hardware are sensitive to differential fault analysis. Moreover, it has been demonstrated that even a single fault during encryption or decryption could cause a large number of errors in encrypted or decrypted data. Although techniques such as iterative and parallel architectures have been explored for fault detection to protect AES encryption and decryption, it is necessary to explore other techniques such as pipelining. Furthermore, balancing a high throughput, reducing low power consumption, and using fewer hardware resources in the pipeline design are great challenges, and they are more difficult when considering fault detection and correction. In this research, we propose a novel hybrid pipeline hardware architecture focusing on error and fault detection for the AES cryptographic algorithm. The architecture is hybrid because it combines hardware and time redundancy through a pipeline structure, analyzing and balancing the critical path and distributing the processing elements within each stage. The main contribution is to present a pipeline structure for ciphering five times on the same data blocks, implementing a voting module to verify when an error occurs or when output has correct cipher data, optimizing the process, and using a decision tree to reduce the complexity of all combinations required for evaluating. The architecture is analyzed and implemented on several FPGA technologies, and it reports a throughput of 0.479 Gbps and an efficiency of 0.336 Mbps/LUT when a Virtex-7 is used.

Study of Safe Elliptic Curve Cryptography over Gaussian Integer

2020 ◽  
Vol E103.A (12) ◽  
pp. 1624-1628
Author(s):  
Kazuki NAGANUMA ◽  
Takashi SUZUKI ◽  
Hiroyuki TSUJI ◽  
Tomoaki KIMURA
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
Gaussian Integer

Enhanced Security Authentication of WiMAX using EC3A

2017 ◽  
Vol 7 (8) ◽  
pp. 219
Author(s):  
Mohd Javed ◽  
Khaleel Ahmad ◽  
Ahmad Talha Siddiqui
Keyword(s):  
Cellular Automata ◽  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
Information Rate ◽  
Security Authentication ◽  
Encryption And Decryption ◽  
High Information

WiMAX is the innovation and upgradation of 802.16 benchmarks given by IEEE. It has numerous remarkable qualities, for example, high information rate, the nature of the service, versatility, security and portability putting it heads and shoulder over the current advancements like broadband link, DSL and remote systems. Though like its competitors the concern for security remains mandatory. Since the remote medium is accessible to call, the assailants can undoubtedly get into the system, making the powerless against the client. Many modern confirmations and encryption methods have been installed into WiMAX; however, regardless it opens with up different dangers. In this paper, we proposed Elliptic curve Cryptography based on Cellular Automata (EC3A) for encryption and decryption the message for improving the WiMAX security

Sign in / Sign up

Export Citation Format

Share Document