Modeling and automatic code generation for wireless sensor network applications using model-driven or business process approaches: A systematic mapping study

2017 ◽  
Vol 132 ◽  
pp. 50-71 ◽  
Author(s):  
Sergio Teixeira ◽  
Bruno Alves Agrizzi ◽  
José Gonçalves Pereira Filho ◽  
Silvana Rossetto ◽  
Roquemar de Lima Baldam
2014 ◽  
Vol 602-605 ◽  
pp. 1324-1328 ◽  
Author(s):  
Fa Lu ◽  
Ke Wei Yang ◽  
Shu Teng Zhang ◽  
Guo Xiong Zhan

Executable UML is one of development directions of Model Driven Architecture (MDA). Executable UML is committed to the automatic code generation from UML model. The simulation and testing of the model is realized either by compiling the model or by executing the code it generate. For solving the problem that how to confirm the correctness of executable model, this paper researches the mechanism of executable UML model and explore a verification method based on executable UML. Finally, researches how to apply the executable mechanism of Executable UML to the design and verification of Armored Vehicle Information System (AVIS) through an imaginary combat mission scenario.


Author(s):  
Alessandra Bagnato ◽  
Imran Quadri ◽  
Etienne Brosse ◽  
Andrey Sadovykh ◽  
Leandro Soares Indrusiak ◽  
...  

This chapter presents the EU-funded MADES FP7 project that aims to develop an effective model-driven methodology to improve the current practices in the development of real-time embedded systems for avionics and surveillance industries. MADES developed an effective SysML/MARTE language subset, and a set of new tools and technologies that support high-level design specifications, validation, simulation, and automatic code generation, while integrating aspects such as component re-use. This chapter illustrates the MADES methodology by means of a car collision avoidance system case study; it presents the underlying MADES language, the design phases, and the set of tools supporting on one hand model verification and validation and, on the other hand, automatic code generation, which enables the implementation on execution platforms such as state-of-the-art FPGAs.


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