Access pattern-based high-performance main memory system for graph processing on single machines

2020 ◽  
Vol 108 ◽  
pp. 560-573
Author(s):  
Ji-Tae Yun ◽  
Su-Kyung Yoon ◽  
Jeong-Geun Kim ◽  
Shin-Dug Kim
Keyword(s):  
High Performance ◽  
Memory System ◽  
Main Memory ◽  
Graph Processing ◽  
Access Pattern

Scalable high performance main memory system using phase-change memory technology

2009 ◽  
Vol 37 (3) ◽  
pp. 24-33 ◽  
Author(s):  
Moinuddin K. Qureshi ◽  
Vijayalakshmi Srinivasan ◽  
Jude A. Rivers
Keyword(s):  
Phase Change ◽  
High Performance ◽  
Phase Change Memory ◽  
Memory System ◽  
Main Memory ◽  
Change Memory

scholarly journals TA-CLOCK: Tendency-Aware Page Replacement Policy for Hybrid Main Memory in High-Performance Embedded Systems

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1111
Author(s):  
Jun Hyeong Choi ◽  
Kyung Min Kim ◽  
Jong Wook Kwak
Keyword(s):  
Embedded Systems ◽  
High Performance ◽  
Pattern Analysis ◽  
Main Memory ◽  
Replacement Policy ◽  
Low Power Consumption ◽  
Access Pattern ◽  
Write Endurance ◽  
Change Memory

Recently, high-performance embedded systems have adopted phase change memory (PCM) as their main memory because PCMs have attractive advantages, such as non-volatility, byte-addressability, high density, and low power consumption. However, PCMs have disadvantages, such as limited write endurance in each cell and high write latency compared to DRAMs. Therefore, researchers have investigated methods for enhancing the limitations of PCMs. In this paper, we propose a page replacement policy called tendency-aware CLOCK (TA-CLOCK) for the hybrid main memory of embedded systems. To improve the limited write endurance of PCMs, TA-CLOCK classifies the page access tendency of the victim page through access pattern analysis and determines the migration location of the victim page. Through the classification of the page access tendency, TA-CLOCK reduces unnecessary page migrations from DRAMs to PCMs. Unnecessary migrations cause an increase in write operations in PCMs and the energy consumption of the hybrid main memory in embedded systems. Thus, our proposed policy improves the limited write endurance of PCMs and enhances the access latency of the hybrid main memory of embedded systems by classifying the page access tendency. We compared the TA-CLOCK with existing page replacement policies to evaluate its performance. In our experiments, TA-CLOCK reduced the number of write operations in PCMs by 71.5% on average, and it enhanced the energy delay product by 38.3% on average compared with other page replacement policies.

scholarly journals CEPRAM: Compression for Endurance in PCM RAM

2017 ◽  
Vol 26 (11) ◽  
pp. 1750167
Author(s):  
Rodrigo Gonzalez-Alberquilla ◽  
Fernando Castro ◽  
Luis Pinuel ◽  
Francisco Tirado
Keyword(s):  
Phase Change ◽  
High Performance ◽  
Memory System ◽  
Main Memory ◽  
Compression Algorithm ◽  
Simulation Results

We deal with the endurance problem of Phase Change Memories (PCM) by proposing Compression for Endurance in PCM RAM [Formula: see text]CEPRAM[Formula: see text], a technique to elongate the lifespan of PCM-based main memory through compression. We introduce a total of three compression schemes based on already existent schemes, but targeting compression for PCM-based systems. We do a two-level evaluation. First, we quantify the performance of the compression, in terms of compressed size, bit-flips and how they are affected by errors. Next, we simulate these parameters in a statistical simulator to study how they affect the endurance of the system. Our simulation results reveal that our technique, which is built on top of Error Correcting Pointers (ECP) but using a high-performance cache-oriented compression algorithm modified to better suit our purpose, manages to further extend the lifetime of the memory system. In particular, it guarantees that at least half of the physical pages are in usable condition for 25% longer than ECP, which is slightly more than 5% more than a scheme that can correct 16 failures per block.

VGL: a high-performance graph processing framework for the NEC SX-Aurora TSUBASA vector architecture

2021 ◽  
Author(s):  
Ilya V. Afanasyev ◽  
Vladimir V. Voevodin ◽  
Kazuhiko Komatsu ◽  
Hiroaki Kobayashi
Keyword(s):  
High Performance ◽  
Graph Processing ◽  
Processing Framework

scholarly journals Gunrock: a high-performance graph processing library on the GPU

2015 ◽  
Vol 50 (8) ◽  
pp. 265-266 ◽  
Author(s):  
Yangzihao Wang ◽  
Andrew Davidson ◽  
Yuechao Pan ◽  
Yuduo Wu ◽  
Andy Riffel ◽  
...  
Keyword(s):  
High Performance ◽  
Graph Processing
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