Multi-level spatial and temporal tiling for efficient HPC stencil computation on many-core processors with large shared caches

2019 ◽  
Vol 92 ◽  
pp. 903-919 ◽  
Author(s):  
Charles Yount ◽  
Alejandro Duran ◽  
Josh Tobin
Keyword(s):  
Stencil Computation ◽  
Shared Caches ◽  
Multi Level ◽  
Many Core

Automatic Code Generation and Optimization of Large-scale Stencil Computation on Many-core Processors

2021 ◽  
Author(s):  
Mingzhen Li ◽  
Yi Liu ◽  
Hailong Yang ◽  
Yongmin Hu ◽  
Qingxiao Sun ◽  
...  
Keyword(s):  
Code Generation ◽  
Large Scale ◽  
Automatic Code Generation ◽  
Stencil Computation ◽  
Automatic Code ◽  
Many Core

HIGH LATENCY AND CONTENTION ON SHARED L2-CACHE FOR MANY-CORE ARCHITECTURES

2011 ◽  
Vol 21 (01) ◽  
pp. 85-106 ◽  
Author(s):  
MARCO A. Z. ALVES ◽  
HENRIQUE C. FREITAS ◽  
PHILIPPE O. A. NAVAUX
Keyword(s):  
Execution Time ◽  
Chip Multiprocessor ◽  
Cache Memory ◽  
Shared Cache ◽  
Shared Caches ◽  
L2 Cache ◽  
Low Performance ◽  
Many Core

Several studies point out the benefits of a shared L2 cache, but some other properties of shared caches must be considered to lead to a thorough understanding of all chip multiprocessor (CMP) bottlenecks. Our paper evaluates and explains shared cache bottlenecks, which are very important considering the rise of many-core processors. The results of our simulations with 32 cores show low performance when L2 cache memory is shared between 2 or 4 cores. In these two cases, the increase of L2 cache latency and contention are the main causes responsible for the increase of execution time.

scholarly journals A Multi-level Optimization Strategy to Improve the Performance of Stencil Computation

2017 ◽  
Vol 108 ◽  
pp. 1083-1092 ◽  
Author(s):  
Gauthier Sornet ◽  
Fabrice Dupros ◽  
Sylvain Jubertie
Keyword(s):  
Optimization Strategy ◽  
Stencil Computation ◽  
Multi Level
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