Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis

2017 ◽  
Vol 71 ◽  
pp. 89-101 ◽  
Author(s):  
Dipanjan Roy ◽  
Anirban Sengupta
Keyword(s):  
High Level Synthesis ◽  
Ip Core ◽  
High Level

Hardware Implementation of a Neuro-Fuzzy Controller Using High Level Synthesis Tool

MACRo 2015 ◽  
2015 ◽  
Vol 1 (1) ◽  
pp. 183-191 ◽  
Author(s):  
Tibor Tămas ◽  
Sándor Tihamér Brassai
Keyword(s):  
Embedded System ◽  
Fuzzy Inference ◽  
Fuzzy Controller ◽  
Design Flow ◽  
High Level Synthesis ◽  
Ip Core ◽  
Inference System ◽  
System Architectures ◽  
Neuro Fuzzy ◽  
High Level

AbstractThe purpose of this work is to present the design flow and the implementation of a neuro-fuzzy controller Intellectual Property (IP) core, using High Level Synthesis (HLS) tool. The realized IP core is designed for FPGA based embedded system architectures. The implemented control algorithm is a Sugeno model based Adaptive Neuro-Fuzzy Inference System (ANFIS). The optimization possibilities using the HLS tool and the designing of the interfaces for the IP core are presented.

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

2009 ◽  
Vol E92-A (12) ◽  
pp. 3169-3179 ◽  
Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
High Level Synthesis ◽  
High Level
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