Phase-locked loop with DC offset removal for single-phase grid-connected converters

2021 ◽  
Vol 194 ◽  
pp. 106980
Author(s):  
Issam A. Smadi ◽  
Bayan H. Bany Fawaz
Keyword(s):  
Single Phase ◽  
Phase Locked Loop ◽  
Dc Offset ◽  
Grid Connected Converters

scholarly journals DC offset rejection in a frequency-fixed second-order generalized integrator-based phase-locked loop for single-phase grid-connected applications

2022 ◽  
Vol 7 (1) ◽  
Author(s):  
Issam A. Smadi ◽  
Bayan H. Bany Fawaz
Keyword(s):  
Single Phase ◽  
Dynamic Performance ◽  
Phase Error ◽  
Phase Locked Loop ◽  
Second Order ◽  
Frequency Variation ◽  
Grid Voltage ◽  
Dc Offset ◽  
Grid Synchronization ◽  
Grid Connected Converters

AbstractFast and accurate monitoring of the phase, amplitude, and frequency of the grid voltage is essential for single-phase grid-connected converters. The presence of DC offset in the grid voltage is detrimental to not only grid synchronization but also the closed-loop stability of the grid-connected converters. In this paper, a new synchronization method to mitigate the effect of DC offset is presented using arbitrarily delayed signal cancelation (ADSC) in a second-order generalized integrator (SOGI) phase-locked loop (PLL). A frequency-fixed SOGI-based PLL (FFSOGI-PLL) is adopted to ensure better stability and to reduce the complexity compared with other SOGI-based PLLs. A small-signal model of the proposed PLL is derived for the systematic design of proportional-integral (PI) controller gains. The effects of frequency variation and ADSC on the proposed PLL are considered, and correction methods are adopted to accurately estimate grid information. The simulation results are presented, along with comparisons to other single-phase PLLs in terms of settling time, peak frequency, and phase error to validate the proposed PLL. The dynamic performance of the proposed PLL is also experimentally validated. Overall, the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all performance indices, offering an improved solution for precise grid synchronization in single-phase applications.

Single‐phase phase locked loop with DC offset and noise rejection for photovoltaic inverters

2014 ◽  
Vol 7 (9) ◽  
pp. 2288-2299 ◽  
Author(s):  
Slobodan Lubura ◽  
Milomir Šoja ◽  
Srd‐an Lale ◽  
Marko Ikić
Keyword(s):  
Single Phase ◽  
Phase Locked Loop ◽  
Dc Offset ◽  
Noise Rejection ◽  
Phase Phase

scholarly journals An Adaptive Frequency Phase-Locked Loop Based on a Third Order Generalized Integrator

Energies ◽  
2019 ◽  
Vol 12 (2) ◽  
pp. 309 ◽  
Author(s):  
Heng Du ◽  
Qiuye Sun ◽  
Qifu Cheng ◽  
Dazhong Ma ◽  
Xu Wang
Keyword(s):  
Single Phase ◽  
Power Grid ◽  
Phase Locked Loop ◽  
Frequency Change ◽  
Third Order ◽  
Vector Method ◽  
Grid Voltage ◽  
Dc Offset ◽  
Voltage Frequency ◽  
Frequency Changes

In this paper, the basic principle and characteristics of a phase-locked loop (PLL) in a single phase grid-connected system are analyzed, and this paper introduces one type virtual orthogonal voltage vector method based on a third order generalized integrator (TOGI) to construct an alpha and beta static coordinate system. The TOGI structure can eliminate the DC offset in a voltage signal or zero offset in the sampling process, and ensure the amplitude of the virtual orthogonal signal is consistent. At the same time, the adaptive frequency estimation unit is introduced, which can effectively deal with the power grid voltage frequency changes and ensure the accuracy of PLL. MATLAB (R2012a, MathWorks, Natick, MA, USA) is used to simulate the variation of power grid voltage frequency, DC component injection, harmonics injection and other parameters, and the performance of PLL is adequately verified. In addition, a 5kW single-phase energy router experimental platform is built to verify the proposed PLL. The experimental results show that the PLL can well track the frequency change of the grid voltage and eliminate the DC offset, so as to achieve accurate phase tracking.

Optimizing Efficiency Driver Comprising Phase-Locked Loop for the Single-Phase Brushless DC Fan Motor

2012 ◽  
Vol 48 (5) ◽  
pp. 1937-1942 ◽  
Author(s):  
Yie-Tone Chen ◽  
Chun-Lung Chiu ◽  
Zong-Hong Tang ◽  
You-Len Liang ◽  
Ruey-Hsun Liang
Keyword(s):  
Single Phase ◽  
Phase Locked Loop ◽  
Brushless Dc
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