Modelling and performance evaluation of the IEEE 802.11 DCF for real-time control

2012 ◽  
Vol 56 (1) ◽  
pp. 435-447 ◽  
Author(s):  
Guosong Tian ◽  
Yu-Chu Tian
Keyword(s):  
Performance Evaluation ◽  
Real Time ◽  
Ieee 802.11 ◽  
Real Time Control ◽  
Ieee 802.11 Dcf ◽  
802.11 Dcf ◽  
Time Control ◽  
And Performance

Performance evaluation of a full-scale advanced phase isolation ditch process by using real-time control strategies

2014 ◽  
Vol 31 (4) ◽  
pp. 611-618 ◽  
Author(s):  
Hyosoo Kim ◽  
Yejin Kim ◽  
Minsoo Kim ◽  
Wenhua Piao ◽  
Jeasung Gee ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
Real Time ◽  
Control Strategies ◽  
Full Scale ◽  
Real Time Control ◽  
Time Control ◽  
Advanced Phase

scholarly journals Hardware RTOS: Custom Scheduler Implementation Based on Multiple Pipeline Registers and MIPS32 Architecture

Electronics ◽  
2019 ◽  
Vol 8 (2) ◽  
pp. 211 ◽  
Author(s):  
Ionel Zagan ◽  
Vasile Găitan
Keyword(s):  
Real Time ◽  
Response Speed ◽  
Real Time Control ◽  
Shared Resources ◽  
Time Control ◽  
Systems Software ◽  
Switch Operation ◽  
And Performance ◽  
Dynamic Scheduler ◽  
Time Systems

The task context switch operation, the inter-task synchronization and communication mechanisms, as well as the jitter occurred in treating aperiodic events, are crucial factors in implementing real-time operating systems (RTOS). In practice and literature, several solutions can be identified for improving the response speed and performance of real-time systems. Software implementations of RTOS-specific functions can generate significant delays, adversely affecting the deadlines required for certain applications. This paper presents an original implementation of a dedicated processor, based on multiple pipeline registers, and a hardware support for a dynamic scheduler with the following characteristics: performs unitary event management, provides access to architecture shared resources, prioritizes and executes the multiple events expected by the same task. The paper also presents a method through which interrupts are assigned to tasks. Through dedicated instructions, the integrated hardware scheduler implements tasks synchronization with multiple prioritized events, thus ensuring an efficient functioning of the processor in the context of real-time control.

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