High-speed IP address lookup using balanced multi-way trees

2006 ◽  
Vol 29 (11) ◽  
pp. 1927-1935 ◽  
Author(s):  
Hyesook Lim ◽  
Wonjung Kim ◽  
Bomi Lee ◽  
Changhoon Yim
Keyword(s):  
High Speed ◽  
Ip Address ◽  
Ip Address Lookup

scholarly journals A Parallel IP Address Lookup Scheme for High-Speed Routers

2004 ◽  
Vol 11A (5) ◽  
pp. 333-340
Author(s):  
Jaehyung Park ◽  
Min Young Chung ◽  
Jinsoo Kim ◽  
Yonggwan Won
Keyword(s):  
High Speed ◽  
Ip Address ◽  
Ip Address Lookup

scholarly journals Vectored-Bloom Filter for IP Address Lookup: Algorithm and Hardware Architectures

2019 ◽  
Vol 9 (21) ◽  
pp. 4621 ◽  
Author(s):  
Hayoung Byun ◽  
Qingling Li ◽  
Hyesook Lim
Keyword(s):  
High Speed ◽  
High Performance ◽  
Hash Table ◽  
Bloom Filter ◽  
Ip Address ◽  
Behavior Simulation ◽  
Field Programmable ◽  
Ip Address Lookup ◽  
Flexible Architecture ◽  
Timing Simulation

The Internet Protocol (IP) address lookup is one of the most challenging tasks for Internet routers, since it requires to perform packet forwarding at wire-speed for tens of millions of incomming packets per second. Efficient IP address lookup algorithms have been widely studied to satisfy this requirement. Among them, Bloom filter-based approach is attractive in providing high performance. This paper proposes a high-speed and flexible architecture based on a vectored-Bloom filter (VBF), which is a space-efficient data structure that can be stored in a fast on-chip memory. An off-chip hash table is infrequently accessed, only when the VBF fails to provide address lookup results. The proposed architecture has been evaluated through both a behavior simulation with C language and a timing simulation with Verilog. The hardware implementation result shows that the proposed architecture can achieve the throughput of 5 million packets per second in a field programmable gate array (FPGA) operated at 100 MHz.

GENETIC-ALGORITHM MEMORY MINIMISATION FOR DESIGNING RECONFIGURABLE IP ADDRESS LOOKUP ENGINE

2005 ◽  
Vol 05 (01) ◽  
pp. 69-90
Author(s):  
SAEED SHAMSHIRI ◽  
S. MEHDI FAKHRAIE
Keyword(s):  
Genetic Algorithm ◽  
High Speed ◽  
Life Time ◽  
Fixed Number ◽  
Memory Consumption ◽  
Ip Address ◽  
Ip Lookup ◽  
Ip Address Lookup ◽  
Genetic Algorithm Approach ◽  
Number Of Segments

IP address lookup engine is the beating heart of a router. For meeting the requirements of a desirable high-speed router, speed, memory consumption, scalability, and reconfigurability of its IP lookup engine are critical. This paper uses a genetic-algorithm approach to optimise the structure of fixed-stride multibit-trie IP lookup methods. In this work, the genetic algorithm is used first in the design phase as an offline optimisation mechanism. This nature-inspired simulation finds the most memory-efficient configuration of IP address segmentation for a fixed number of address segments. Then, for adapting to network variations, the proposed method dynamically changes the number of address segments to compromise between speed and memory consumption. Each time the number of segments changes, an online genetic program is run to optimise the segmentation. Therefore, the lookup engine reconfigures itself to cover more prefixes during the time. The reconfigurability in response to the network variations, and scalability to the number of prefixes improves the life time of a router that uses this method.

scholarly journals Towards Dynamic and Scalable High-Speed IP Address Lookup Based on B+ Tree

2012 ◽  
Vol E95.D (9) ◽  
pp. 2277-2287 ◽  
Author(s):  
Gang WANG ◽  
Yaping LIN ◽  
Rui LI ◽  
Jinguo LI ◽  
Xin YAO ◽  
...  
Keyword(s):  
High Speed ◽  
Ip Address ◽  
Ip Address Lookup

High speed IP address lookup architecture using hashing

2003 ◽  
Vol 7 (10) ◽  
pp. 502-504 ◽  
Author(s):  
Hyesook Lim ◽  
Ji-Hyun Seo ◽  
Yeo-Jin Jung
Keyword(s):  
High Speed ◽  
Ip Address ◽  
Ip Address Lookup
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