Efficient compact model for calculating the surface potential of carbon-nanotube field-effect transistors using a curve-fitting method

2015 ◽  
Vol 15 (8) ◽  
pp. 938-942
Author(s):  
Jong-Myeon Park ◽  
Shin-Nam Hong
2018 ◽  
Vol 124 (3) ◽  
pp. 034302 ◽  
Author(s):  
Lingfei Wang ◽  
Yang Li ◽  
Xuewei Feng ◽  
Kah-Wee Ang ◽  
Xiao Gong ◽  
...  

2018 ◽  
Vol 123 (6) ◽  
pp. 064501 ◽  
Author(s):  
Jingchen Cao ◽  
Songang Peng ◽  
Wei Liu ◽  
Quantan Wu ◽  
Ling Li ◽  
...  

2007 ◽  
Vol 46 (4B) ◽  
pp. 2496-2500 ◽  
Author(s):  
Takeo Umesaka ◽  
Hirofumi Ohnaka ◽  
Yutaka Ohno ◽  
Shigeru Kishimoto ◽  
Koichi Maezawa ◽  
...  

The goal of this thesis is to develop carbon nanotube field effect transistors (CNFETs) based static random-access memory (SRAM) and implement it into a Very-highspeed integrated circuit Hardware Description Language Analog and Mixed-Signal (VHDLAMS). To achieve this objective, a compact model of the transistor known as enhancementmode MOSFET-like SWCNT-CNFET is used. This circuit-compatible model of CNFET is described using VHDL-AMS and tested for basic electrical characteristics. This model is valid for CNFETs with channel lengths greater than 20 nm. Based on the CNFETs a new SRAM is designed, and implemented in VHDL-AMS. The performance of the proposed SRAM cell is investigated and compared with SRAMs from conventional metal-oxide semiconductor field effect transistors (MOSFETs). The effect of substrate biasing a CNFET is also demonstrated and implemented in designing the SRAM cell. The VHDL-AMS codes of the CNFET and the SRAM are simulated in software known as Ansoft Simplorer. The compact model of the CNFET is organized hierarchically in three main levels. The first level models the intrinsic channel just beneath the gate of the transistor. The second level builds upon the first level and models the doped source and drain regions of the CNFET. The last level represents the complete trans-capacitance model of the transistor and accounts for multiple CNTs. The proposed SRAM cell is composed of four CNFETs and two load resistors. The driver CNFETs of the proposed SRAM cell are substrate biased. Besides, 8-bit complete SRAM architecture based on this cell is indicated. The performance analysis of the SRAM shows that it has better writing and reading speed as well as better stability when compared with SRAM from conventional MOSFETs. Specifically, the newly proposed SRAM cell has read time of twenty five pico seconds, write time of twenty pico seconds and can tolerate a noise of 120 mV at 32 nm node technology.


2012 ◽  
Vol 19 (2) ◽  
pp. 381-394
Author(s):  
José Pereira ◽  
Octavian Postolache ◽  
Pedro Girão

Using A Segmented Voltage Sweep Mode and A Gaussian Curve Fitting Method to Improve Heavy Metal Measurement System PerformanceThis paper presents a voltammetric segmented voltage sweep mode that can be used to identify and measure heavy metals' concentrations. The proposed sweep mode covers a set of voltage ranges that are centered around the redox potentials of the metals that are under analysis. The heavy metal measurement system can take advantage of the historical database of measurements to identify the metals with higher concentrations in a given geographical area, and perform a segmented sweep around predefined voltage ranges or, alternatively, the system can perform a fast linear voltage sweep to identify the voltammetric current peaks and then perform a segmented voltage sweep around the set of voltages that are associated with the voltammetric current peaks. The paper also includes the presentation of two auto-calibration modes that can be used to improve system's reliability and proposes the usage of a Gaussian curve fitting of voltammetric data to identify heavy metals and to evaluate their concentrations. Several simulation and experimental results, that validate the theoretical expectations, are also presented in the paper.


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