Study of the energy distribution of the interface trap density in a GeSn MOS structure by numerical simulation of the electrical characteristics

2014 ◽  
Vol 291 ◽  
pp. 25-30 ◽  
Author(s):  
B. Baert ◽  
M. Schmeits ◽  
N.D. Nguyen
Keyword(s):  
Numerical Simulation ◽  
Energy Distribution ◽  
Trap Density ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Electrical Characteristics ◽  
Mos Structure

The Electrical Characteristics of a Pd/AlN/Si Thin Film Hydrogen Gas Sensor

2003 ◽  
Vol 801 ◽  
Author(s):  
Erik F. McCullen ◽  
Haripriya E. Prakasam ◽  
Wenjun Mo ◽  
Jagdish Thakur ◽  
Ratna Naik ◽  
...  
Keyword(s):  
Thin Film ◽  
Surface States ◽  
Hydrogen Gas ◽  
Trap Density ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Interface Traps ◽  
Electrical Characteristics ◽  
Film Sensor ◽  
Si Thin Film

ABSTRACTWe have extended our previous investigation of the electrical characteristics of a Pd/AlN/Si thin film sensor for varying thicknesses of AlN, from 300–2000Å. The capacitance vs. voltage, C(V), and conductance vs. voltage, G(V), measurements were utilized to investigate the presence of surface states within the Si gap at the AlN/Si interface. Our previous experiments on 500Å AlN did show the presence of interface traps, with an estimated surface density between 8×1014 and 1.5×1015 m−2eV−1 [1]. In our present work we've examined the effect of AlN thickness on the density of these interface traps. The density is dependent on AlN thickness. The thinner devices, 300Å, showed an interface trap density of 20–30×1015 m−2eV−1. The interface trap density decreased with increasing thickness up to 500Å, where the density remained relatively constant at about 1–5×1015 m−2eV−1 for thicknesses up to 2000Å. We have also shown that the interface trap density is independent of annealing.

Investigation of the Interface Quality and Reliability of 4H-SiC MOS Structure with NO and Forming Gas Annealing Treatment

2016 ◽  
Vol 858 ◽  
pp. 647-650
Author(s):  
Zhao Yang Peng ◽  
Yi Yu Wang ◽  
Hua Jun Shen ◽  
Yun Bai ◽  
Yi Dan Tang ◽  
...  
Keyword(s):  
Barrier Height ◽  
Dielectric Breakdown ◽  
Annealing Treatment ◽  
Trap Density ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Interface Quality ◽  
Mos Capacitors ◽  
Mos Structure ◽  
Quality And Reliability

Effects of NO and forming gas annealing treatment on the interface quality and reliability of 4H-SiC MOS were systematically studied by low temperature conductance measurements in combination with time-zero dielectric breakdown and time-dependent dielectric breakdown methods. The interface trap density (Dit) showed no obvious reduction after forming gas annealing, and the values of Dit decreased significantly after combined NO and forming gas annealing treatment. The F-N barrier height, electric field to breakdown (Ebd) and charge to breakdown (Qbd) of the MOS structure increased from 2.42 eV, 10 MV/cm, 1mC/cm2 to 2.62 eV, 10.7 MV/cm, 78mC/cm2 after forming gas annealing. The values of F-N barrier height, Ebd and Qbd for MOS capacitors with combined NO and forming gas annealing treatment are 2.69 eV, 10.2 MV/cm, and 24mC/cm2. These results suggest that forming gas annealing is more effective in reliability improvement. While when considering the interface trap density, it seems that combined NO and forming gas annealing treatment is a better choice.

Analyzing the interface trap density in SiGe capacitors using an abnormal flat band voltage shift at low temperature

2020 ◽  
Vol 13 (11) ◽  
pp. 111006
Author(s):  
Li-Chuan Sun ◽  
Chih-Yang Lin ◽  
Po-Hsun Chen ◽  
Tsung-Ming Tsai ◽  
Kuan-Ju Zhou ◽  
...  
Keyword(s):  
Low Temperature ◽  
Trap Density ◽  
Flat Band ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Flat Band Voltage ◽  
Voltage Shift

Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs

2007 ◽  
Vol 28 (3) ◽  
pp. 232-234 ◽  
Author(s):  
G. Kapila ◽  
B. Kaczer ◽  
A. Nackaerts ◽  
N. Collaert ◽  
G. V. Groeseneken
Keyword(s):  
Direct Measurement ◽  
Trap Density ◽  
Interface Trap Density ◽  
Interface Trap

On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates

2008 ◽  
Vol 55 (2) ◽  
pp. 547-556 ◽  
Author(s):  
Koen Martens ◽  
Chi On Chui ◽  
Guy Brammertz ◽  
Brice De Jaeger ◽  
Duygu Kuzum ◽  
...  
Keyword(s):  
High Mobility ◽  
Trap Density ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Mos Devices ◽  
Semiconductor Substrates

scholarly journals Interface trap density and mobility extraction in InGaAs buried quantum well metal-oxide-semiconductor field-effect-transistors by gated Hall method

2014 ◽  
Vol 104 (13) ◽  
pp. 131605 ◽  
Author(s):  
Thenappan Chidambaram ◽  
Dmitry Veksler ◽  
Shailesh Madisetti ◽  
Andrew Greene ◽  
Michael Yakimov ◽  
...  
Keyword(s):  
Quantum Well ◽  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Trap Density ◽  
Oxide Semiconductor ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Hall Method

Interface trap density in amorphous La2Hf2O7/SiO2 high-κ gate stacks on Si

2005 ◽  
Vol 80 (2) ◽  
pp. 253-257 ◽  
Author(s):  
B. Mereu ◽  
A. Dimoulas ◽  
G. Vellianitis ◽  
G. Apostolopoulos ◽  
R. Scholz ◽  
...  
Keyword(s):  
Trap Density ◽  
Interface Trap Density ◽  
Interface Trap ◽  
Gate Stacks
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