scholarly journals On-chip genotoxic bioassay based on bioluminescence reporter system using three-dimensional microfluidic network

2006 ◽  
Vol 560 (1-2) ◽  
pp. 24-29 ◽  
Author(s):  
Koji Maehana ◽  
Hirofumi Tani ◽  
Tamio Kamidate
Keyword(s):  
Three Dimensional ◽  
Reporter System ◽  
Microfluidic Network ◽  
On Chip

scholarly journals Electromechanically reconfigurable optical nano-kirigami

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Shanshan Chen ◽  
Zhiguang Liu ◽  
Huifeng Du ◽  
Chengchun Tang ◽  
Chang-Yin Ji ◽  
...  
Keyword(s):  
Near Infrared ◽  
Large Range ◽  
Three Dimensional ◽  
High Contrast ◽  
Si Substrate ◽  
High Modulation ◽  
Gold Nanostructure ◽  
Infrared Wavelengths ◽  
On Chip ◽  
Nano Electromechanical System

AbstractKirigami, with facile and automated fashion of three-dimensional (3D) transformations, offers an unconventional approach for realizing cutting-edge optical nano-electromechanical systems. Here, we demonstrate an on-chip and electromechanically reconfigurable nano-kirigami with optical functionalities. The nano-electromechanical system is built on an Au/SiO2/Si substrate and operated via attractive electrostatic forces between the top gold nanostructure and bottom silicon substrate. Large-range nano-kirigami like 3D deformations are clearly observed and reversibly engineered, with scalable pitch size down to 0.975 μm. Broadband nonresonant and narrowband resonant optical reconfigurations are achieved at visible and near-infrared wavelengths, respectively, with a high modulation contrast up to 494%. On-chip modulation of optical helicity is further demonstrated in submicron nano-kirigami at near-infrared wavelengths. Such small-size and high-contrast reconfigurable optical nano-kirigami provides advanced methodologies and platforms for versatile on-chip manipulation of light at nanoscale.

scholarly journals High-Performance On-Chip Silicon Beamsplitter Based on Subwavelength Metamaterials for Enhanced Fabrication Tolerance

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1304
Author(s):  
Raquel Fernández de Cabo ◽  
David González-Andrade ◽  
Pavel Cheben ◽  
Aitor V. Velasco
Keyword(s):  
Integrated Circuits ◽  
Fundamental Mode ◽  
High Performance ◽  
Three Dimensional ◽  
High Sensitivity ◽  
Power Splitting ◽  
Excess Loss ◽  
Power Splitters ◽  
On Chip ◽  
Efficient Power

Efficient power splitting is a fundamental functionality in silicon photonic integrated circuits, but state-of-the-art power-division architectures are hampered by limited operational bandwidth, high sensitivity to fabrication errors or large footprints. In particular, traditional Y-junction power splitters suffer from fundamental mode losses due to limited fabrication resolution near the junction tip. In order to circumvent this limitation, we propose a new type of high-performance Y-junction power splitter that incorporates subwavelength metamaterials. Full three-dimensional simulations show a fundamental mode excess loss below 0.1 dB in an ultra-broad bandwidth of 300 nm (1400–1700 nm) when optimized for a fabrication resolution of 50 nm, and under 0.3 dB in a 350 nm extended bandwidth (1350–1700 nm) for a 100 nm resolution. Moreover, analysis of fabrication tolerances shows robust operation for the fundamental mode to etching errors up to ± 20 nm. A proof-of-concept device provides an initial validation of its operation principle, showing experimental excess losses lower than 0.2 dB in a 195 nm bandwidth for the best-case resolution scenario (i.e., 50 nm).

A new efficient multi‐task applications mapping for three‐dimensional Network‐on‐Chip based MPSoC

2021 ◽  
Author(s):  
Khadidja Gaffour ◽  
Mohammed Kamel Benhaoua ◽  
Abou El Hassan Benyamina ◽  
Amit Kumar Singh
Keyword(s):  
Three Dimensional ◽  
Network On Chip ◽  
Dimensional Network ◽  
On Chip

Current and Future Three-Dimensional LSI Integration Technology by “chip on chip”, “chip on wafer” and “wafer on wafer”

2006 ◽  
Vol 970 ◽  
Author(s):  
Manabu Bonkohara ◽  
Makoto Motoyoshi ◽  
Kazutoshi Kamibayashi ◽  
Mitsumasa Koyanagi
Keyword(s):  
Three Dimensional ◽  
Process Time ◽  
Future Technology ◽  
Sensor Device ◽  
Research Level ◽  
Key Technologies ◽  
The Future ◽  
Chip Size ◽  
On Chip ◽  
Chip Chip

ABSTRACTRecently the development of three dimensional LSI (3D-LSI) has been accelerated and its stage has changed from the research level or limited production level to the investigation level with a view to mass production. This paper describes the current and the future 3D-LSI technologies which we have considered and imagined. The current technology is taken our Chip Size Package (CSP) for sensor device, for instance. In the future technology, there are the five key technologies are described. And considering con and pro of the current 3D LSI stacked approach, such as CoC (Chip on Chip), CoW (Chip on Wafer) and WoW (Wafer on Wafer), We confirmed that CoW combined with Super-Smart-Stack (SSS™) technology will shorten the process time per chip at the same level as WoW approach and is effective to minimize process cost.

Three-dimensional tissue model in direct contact with an on-chip vascular bed enabled by removable membranes

Lab on a Chip ◽  
2022 ◽  
Author(s):  
Yoshikazu Kameda ◽  
Surachada Chuaychob ◽  
Miwa Tanaka ◽  
Yang Liu ◽  
Ryu Okada ◽  
...  
Keyword(s):  
Tissue Culture ◽  
Direct Contact ◽  
Three Dimensional ◽  
Culture Period ◽  
Tissue Model ◽  
Vascular Bed ◽  
On Chip

Three-dimensional (3D) tissue culture is a powerful tool for understanding physiological events. However, 3D tissues still have limitations in their size, culture period, and maturity, which are caused by the...

Analytical Modeling of Temperature Distribution in Interposer-Based Microelectronic Systems

2013 ◽  
Author(s):  
Leila Choobineh ◽  
Dereje Agonafer ◽  
Ankur Jain
Keyword(s):  
Heat Transfer ◽  
Finite Element ◽  
Temperature Field ◽  
Temperature Distribution ◽  
Analytical Modeling ◽  
Three Dimensional ◽  
Heat Transfer Process ◽  
Thermal Design ◽  
Research Attention ◽  
On Chip

Heterogeneous integration in microelectronic systems using interposer technology has attracted significant research attention in the past few years. Interposer technology is based on stacking of several heterogeneous chips on a common carrier substrate, also referred to as the interposer. Compared to other technologies such as System-on-Chip (SoC) or System-in-Package (SiP), interposer-based integration offers several technological advantages. However, the thermal management of an interposer-based system is not well understood. The presence of multiple heat sources in various die and the interposer itself needs to be accounted for in any effective thermal model. While a finite-element based simulation may provide a reasonable temperature prediction tool, an analytical solution is highly desirable for understanding the fundamentals of the heat transfer process in interposers. In this paper, we describe our recent work on analytical modeling of heat transfer in interposer-based microelectronic systems. The basic governing energy conservation equations are solved to derive analytical expressions for the temperature distribution in an interposer-based microelectronic system. These solutions are combined with an iterative approach to provide the three-dimensional temperature field in an interposer. Results are in excellent agreement with finite-element solutions. The analytical model is utilized to study the effect of various parameters on the temperature field in an interposer system. Results from this work may be helpful in the thermal design of microelectronic systems containing interposers.

Sign in / Sign up

Export Citation Format

Share Document