MorphoSys: a reconfigurable processor targeted to high performance image application

1999 ◽  
pp. 661-669 ◽  
Author(s):  
Guangming Lu ◽  
Ming-hau Lee ◽  
Hartej Singh ◽  
Nader Bagherzadeh ◽  
Fadi J. Kurdahi ◽  
...  
Keyword(s):  
High Performance ◽  
Reconfigurable Processor

scholarly journals CHiPReP—A Compiler for the HiPReP High-Performance Reconfigurable Processor

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2590
Author(s):  
Markus Weinhardt ◽  
Mohamed Messelka ◽  
Philipp Käsgen
Keyword(s):  
High Performance ◽  
Optimization Method ◽  
Coarse Grained ◽  
Splitting Algorithm ◽  
Reconfigurable Processor ◽  
Routing Optimization ◽  
Integrated Placement ◽  
Reconfigurable Array ◽  
Address Generator ◽  
Scheduling Heuristic

This article presents CHiPReP, a C compiler for the HiPReP processor, which is a high-performance Coarse-Grained Reconfigurable Array employing Floating-Point Units. CHiPReP is an extension of the LLVM and CCF compiler frameworks. Its main contributions are (i) a Splitting Algorithm for Data Dependence Graphs, which distributes the computations of a C loop to Address-Generator Units and Processing Elements; (ii) a novel instruction clustering and scheduling heuristic; and (iii) an integrated placement, pipeline balancing and routing optimization method based on Simulated Annealing. The compiler was verified and analyzed using a cycle-accurate HiPReP simulation model.

scholarly journals Design and implementation of high performance matrix inversion based on reconfigurable processor

2016 ◽  
Vol 13 (15) ◽  
pp. 20160579-20160579 ◽  
Author(s):  
Kun Wang ◽  
Li Li ◽  
Feng Han ◽  
Fan Feng ◽  
Jun Lin
Keyword(s):  
High Performance ◽  
Matrix Inversion ◽  
Reconfigurable Processor ◽  
Design And Implementation ◽  
Performance Matrix

H.264/AVC Intra Predictor on a Coarse-Grained Reconfigurable Multi-Media System

2012 ◽  
Vol 546-547 ◽  
pp. 469-474
Author(s):  
Xing Wang ◽  
Lei Bo Liu ◽  
Shou Yi Yin ◽  
Min Zhu ◽  
Shao Jun Wei
Keyword(s):  
High Performance ◽  
Coarse Grained ◽  
Reconfigurable Architectures ◽  
Prediction Algorithm ◽  
Worst Case ◽  
Reconfigurable Processor ◽  
High Profile ◽  
Media System ◽  
Multi Media ◽  
Simulation Results

Coarse-Grained Reconfigurable Architectures (CGRA) have proved to be the potential candidates to meet the high performance, low power and flexibility required by embedded systems. In this paper, we implemented a High Profile Intra Predictor for H.264/AVC decoder on a novel coarse-grained reconfigurable processor- Remus (Reconfigurable Multi-media System). We proposed the pipeline and parallel scheduling process for intra prediction algorithm and the simulation results show that 548 clock cycles are consumed for the worst case of intra macro blocks.

scholarly journals Reconfigurable Morphological Processor for Grayscale Image Processing

Electronics ◽  
2021 ◽  
Vol 10 (19) ◽  
pp. 2429
Author(s):  
Bin Zhang
Keyword(s):  
Image Processing ◽  
Embedded Systems ◽  
High Performance ◽  
Morphological Processing ◽  
Process Synthesis ◽  
Morphological Operations ◽  
Grayscale Image ◽  
Reconfigurable Processor ◽  
System Clock ◽  
Processing Module

Grayscale morphology is a powerful tool in image, video, and visual applications. A reconfigurable processor is proposed for grayscale image morphological processing. The architecture of the processor is a combination of a reconfigurable grayscale processing module (RGPM) and peripheral circuits. The RGPM, which consists of four grayscale computing units, conducts grayscale morphological operations and implements related algorithms of more than 100 f/s for a 1024 × 1024 image. The periphery circuits control the entire image processing and dynamic reconfiguration process. Synthesis results show that the proposed processor can provide 43.12 GOPS and achieve 8.87 GOPS/mm2 at a 220-MHz system clock. The simulation and experimental results show that the processor is suitable for high-performance embedded systems.

scholarly journals High Performance Reconfigurable Elliptic Curve Cipher Processor Implementation

2021 ◽  
Vol 2136 (1) ◽  
pp. 012043
Author(s):  
Jian Zhang ◽  
Liting Niu
Keyword(s):  
Elliptic Curve ◽  
High Performance ◽  
Optimization Design ◽  
Computing Time ◽  
Communication Security ◽  
Modular Multiplication ◽  
Clock Frequency ◽  
Reconfigurable Processor ◽  
Binary Fields ◽  
Key Length

Abstract Elliptic Curve Encryption (ECC) has been widely used in the field of digital signatures in communication security. ECC standards and the diversification of application scenarios put forward higher requirements for the flexibility of ECC processors. Therefore, it is necessary to design a flexible and reconfigurable processor to adapt to changing standards. The cryptographic processor chip designed in this paper supports the choice of prime and binary fields, supports the maximum key length of 576 bits, uses microcode programming to achieve reconfigurable function, and significantly improves the flexibility of the dedicated cryptographic processor. At the same time, the speed of modular multiplication and modular division can be greatly improved under the condition of keeping the low level of hardware resources through a carefully designed modular unit of operation. After using FPGA for hardware implementation, it is configured into a 256-bit key length. The highest clock frequency of this design can reach 55.7MHz, occupying 12425LUTS. Compared with a similar design, the performance is also greatly improved. After MALU module optimization design, modular multiplication module division also has significant advantages in computing time consumption.

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