Network complexity of sorting and graph problems and simulating CRCW PRAMS by interconnection networks

New protocol for multistage interconnection networks

IEE Proceedings E Computers and Digital Techniques ◽

10.1049/ip-e.1991.0035 ◽

1991 ◽

Vol 138 (4) ◽

pp. 269

Author(s):

N.M. Patel

Keyword(s):

Interconnection Networks ◽

Multistage Interconnection Networks

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Dual parameterization and parameterized approximability of subset graph problems

RAIRO - Operations Research ◽

10.1051/ro/2016018 ◽

2017 ◽

Vol 51 (1) ◽

pp. 261-266 ◽

Cited By ~ 1

Author(s):

Édouard Bonnet ◽

Vangelis Th. Paschos

Keyword(s):

Graph Problems

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Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks

IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ◽

10.1587/transfun.e94.a.2412 ◽

2011 ◽

Vol E94-A (11) ◽

pp. 2412-2424 ◽

Cited By ~ 1

Author(s):

Po-Tsang HUANG ◽

Wei HWANG

Keyword(s):

Interconnection Networks ◽

Buffer Design ◽

On Chip

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Efficient Instruction and Data Caching for High Performance Embedded Processors

Jornada de Jóvenes Investigadores del I3A ◽

10.26754/jji-i3a.201201788 ◽

1970 ◽

pp. 9

Author(s):

A. Ferrerón Labari ◽

D. Suárez Gracia ◽

V. Viñals Yúfera

Keyword(s):

Embedded Systems ◽

Power Consumption ◽

Low Power ◽

Interconnection Networks ◽

High Performance ◽

Critical Issue ◽

Content Management ◽

Structure Design ◽

Portable Devices ◽

On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

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