PM1 and PMLisp: An experimental machine and its lisp system for research on MIMD massively parallel computation

1990 ◽  
pp. 322-347 ◽  
Author(s):  
Taiichi Yuasa ◽  
Takafumi Kawana
Keyword(s):  
Parallel Computation ◽  
Massively Parallel

scholarly journals Trade-Off Considerations in Designing Efficient VLSI Feasible Interconnection Networks

VLSI Design ◽  
1995 ◽  
Vol 2 (4) ◽  
pp. 365-374 ◽  
Author(s):  
S. Q. Zheng ◽  
B. Cong ◽  
S. Bettayeb
Keyword(s):  
Parallel Computation ◽  
Interconnection Networks ◽  
Hybrid Networks ◽  
Massively Parallel ◽  
Star Graph ◽  
Trade Off ◽  
Vlsi Technology ◽  
Massively Parallel Computing ◽  
Better Than ◽  
Simple Combination

It is well known that the hypercube has a rich set of good properties, and consequently it has been recognized an ideal structure for parallel computation. Nevertheless, according to the current VLSI technology, the implementation feasibility of the hypercube remains questionable when the size of the hypercube becomes large. Recent research efforts have been concentrated on finding good alternatives to the hypercube. The star graph was shown having many desirable properties of the hypercube, and in several aspects, the star graph is better than the hypercube. However, we observe that the star graph as a network has several disadvantages, compared with the hypercube. In this paper, we propose a class of new networks, the star-hypercube hybrid networks (or the SH networks). The SH network is a simple combination of both the star graph and the hypercube. This class of networks contains the star graph and the hypercube as subclasses. We show that the SH network is an efficient and versatile network for parallel computation, since it shares properties of both the hypercube and the star graph, and remedies several major disadvantages of the hypercube and the star graph. This class of networks provide more flexibility in choosing the size, degree, number of vertices, degree of fault tolerance, etc. in designing massively parallel computing structures feasible for VLSI implementations.

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