Processing Unit for Stacked Optical Computing System: Pattern Shift Encoder

1996 ◽  
Vol 3 (6) ◽  
pp. A381-A384 ◽  
Author(s):  
Hideo Kawai ◽  
Yoshinori Takeuchi
Keyword(s):  
Optical Computing ◽  
Computing System ◽  
Processing Unit

A Novel Approach to Design a 4-Bit Binary Comparator Circuit with Reversible Logic using CDSM Gate

2015 ◽  
Vol 11 (1) ◽  
pp. 36-49
Author(s):  
Vandana Shukla ◽  
O. P. Singh ◽  
G. R. Mishra ◽  
R. K. Tiwari
Keyword(s):  
Low Power ◽  
Power Loss ◽  
Optical Computing ◽  
Logic Gates ◽  
Digital Circuit ◽  
Reversible Logic ◽  
Processing Unit ◽  
Quantum Cost ◽  
Central Processing ◽  
Control Circuits

In the recent scenario of microelectronic industry, the reversible logic is considered as the burgeonic technology for digital circuit designing. It deals with the aim to generate digital circuits with zero power loss characteristics. Optical computing, Nanotechnology, Low power CMOS design and Digital Signal Processing (DSP) processors are leading areas of development with the concept of reversible logic. Researchers have already proposed various subsystems of the computer for the creation of low power loss devices with the help of numerous available reversible logic gates. Here in this paper, the authors have proposed a new reversible gate named as CDSM gate with 4×4 size. This CDSM gate is used to design optimized 4-bit binary comparator. The optimization is improved as compared to the existing designs based on some significant performance parameters such as total number of gates, garbage outputs generated, constant inputs and quantum cost. Comparators are widely used in various computing applications such as counters, convertor, Central Processing Unit (CPU) and control circuits etc. The comparator circuits using reversible logic can be visualized as a low power loss subsystem for the development of improved digital systems.

MOBILE COMPUTING WITH PERSONAL AREA NETWORK AND HUMAN POWER GENERATION

2005 ◽  
Vol 15 (02) ◽  
pp. 169-175 ◽  
Author(s):  
ADRIAN DAVID CHEOK ◽  
MAN FUNG HO ◽  
EVA YUSTINA ◽  
SHANG PING LEE
Keyword(s):  
Power Generation ◽  
Mobile Computing ◽  
Computing System ◽  
Human Motion ◽  
Area Network ◽  
Processing Unit ◽  
Wearable Computer ◽  
Human Power ◽  
Wide Range ◽  
Personal Area Network

For mobile computing system such as wearable computer, one of the most critical hardware issues is the provision of electric power. Various different sources of power for wearable computer have been investigated; however, we are interested only in power that can be generated in-situ, such as human power. This paper describes a novel mean of multiple source human power generation for small wearable electronic devices, and then demonstrates the digital information transfer between wearable computing devices by using human skin as "antenna". There are a wide range of peripheral devices in a mobile computing system, such as sensors and identification memory tags. As the amount of such devices increases in a mobile computing design, there is a need for these devices to communicate efficiently with the central processing unit. Also, it is highly desirable that these devices could be conveniently connected to the wearable computer without many dangling wires. We developed a personal area network (PAN) system which attempts to interconnect such devices, and at the same time uses human body as communication channel. This system is in a way novel because it is totally powered by human motion.

scholarly journals All-Optical Logic and Arithmetic Operators Designed by Modified Add-Drop Filter

2018 ◽  
Vol 12 (1) ◽  
pp. 73-80
Author(s):  
Prapas Phongsanam ◽  
Preecha Yupapin
Keyword(s):  
Optical Computing ◽  
Full Adder ◽  
Computing System ◽  
Ring Resonators ◽  
Small Scale ◽  
Optical Logic ◽  
Optical Elements ◽  
Half Adder ◽  
Compact Size ◽  
All Optical

Optical micro-ring resonators (MRRs) element can be used in many applications. This paper we propose a photonics circuit design based on optical tree architecture (OTA) for all-optical elements by using the modified add-drop filter for an all-optical arithmetic logic unit (ALU) aimed for computing applications system. All-optical 2x4 decoder, all-optical comparator, all-optical half adder, all-optical half subtractor, all-optical full adder, all-optical full subtractor and proposed new design all-optical 4x16 decoder were proposed. We have studied the nonlinear effect in the modified add-drop filter system, which is control by injected the nonlinear pulses on top as an input for generated all-optical logic and arithmetic operations simultaneously at the through and drop port of modified add-drop filter. The optical input and control field of the modified add-drop filter circuit can be formed by nonlinear dark and bright pluses. The obtained simulation results have shown that the nonlinear pulse generated by the nonlinear modified add-drop filter can control the output consistency, which is important when the interconnect between each circuit output parts are required. The advantages of the modified add-drop filter are low power, ultra-fast switching, tuneable and high security which is compact size and footprint. It is suitable for the next generation of all-optical small-scale device and all-optical computing system requirements.

scholarly journals Modeling and simulation of a nanoscale optical computing system

2014 ◽  
Vol 74 (6) ◽  
pp. 2470-2483 ◽  
Author(s):  
Jun Pang ◽  
Alvin R. Lebeck ◽  
Christopher Dwyer
Keyword(s):  
Modeling And Simulation ◽  
Optical Computing ◽  
Computing System

Hardware Design for Novel Packaging of Multi-Cellular Meta-Processing Unit

2010 ◽  
Vol 2010 (1) ◽  
pp. 000528-000532
Author(s):  
Son Nguyen ◽  
Joan Delalic ◽  
Bjorn Gruenwald
Keyword(s):  
High Speed ◽  
Control Unit ◽  
Computing System ◽  
Internal Clock ◽  
Order System ◽  
Processing Unit ◽  
Centralized Control ◽  
Self Similarity ◽  
Multiple Cells ◽  
Self Organizing

Multi-cellular meta-processing unit is an assembly of a large number of small processors organized in self-similarity configurations, together capable of executing trillions of instructions per second. Multiple cells (small processors) are self-organizing processes that are inherently self-similar. Each cell has multiple independent, high speed serial I/O channels. Each cell has its own internal clock, so each cell runs at a slightly different speed as there is no synchronization between any of the cells. Each cell in an n-order system is connected to n−1 peers (neighbors at its own level) and one to the next higher level. This paper presents a package of 9 computing cells (PC/104-Plus LX800 SBC) grouped in three. So each cell is connected to 2 peers and 1 next higher level, and each loaded with its own operating system (Hilbert Engine). The 9 cells can work independently without a centralized control unit. The advantage of this new approach lies in extremely high execution capability in processing a given program. Additionally, the system is self-organizing, which means that the multitude of computing cells is transparent to the user. The system can be treated as a single or few input entities. The advantages of this system include scalability, ultra-high throughput, and fabrication of a large number of small computing cells on single or multiple Si wafers, and multiple wafers will be stacked together to enlarge the capability of the computing system.

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