The formation of low resistance electrical contacts to shallow junction InP devices without compromising emitter integrity

1991 ◽  
Vol 20 (7) ◽  
pp. 875-880 ◽  
Author(s):  
Navid S. Fatemi ◽  
Victor G. Weizer
Keyword(s):  
Electrical Contacts ◽  
Shallow Junction ◽  
Low Resistance

Optimization of Ti and Co Self-Aligned Silicide RTP for 0.10 μm Cmos

1998 ◽  
Vol 525 ◽  
Author(s):  
J. A. Kittl ◽  
Q. Z. Hong ◽  
H. Yang ◽  
N. Yu ◽  
M. Rodder ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Sheet Resistance ◽  
Cmos Technology ◽  
Successful Implementation ◽  
Optimal Process ◽  
Shallow Junction ◽  
Low Resistance ◽  
Mo Doping ◽  
One Step

ABSTRACTAs CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

Low-Resistance Electrical Contacts to p-Type GaN by Using InxGa1-xN Cap Layers

2001 ◽  
Vol 693 ◽  
Author(s):  
Th. Gessmann ◽  
Y.-L. Li ◽  
J. W. Graff ◽  
E. F. Schubert ◽  
J. K. Sheu
Keyword(s):  
Contact Resistance ◽  
Electric Fields ◽  
Ohmic Contacts ◽  
Electrical Contacts ◽  
Specific Contact Resistance ◽  
Low Resistance ◽  
Transmission Line Method ◽  
Specific Contact ◽  
P Type ◽  
20 Nm

AbstractA novel type of low-resistance ohmic contacts is demonstrated utilizing polarization-induced electric fields in thin p-type InGaN layers on p-type GaN. An increase of the hole tunneling probability through the barrier and a concomitant significant decrease of the specific contact resistance can be attributed to a reduction of the tunneling barrier width in the InGaN capping layers due to the polarization-induced electric fields. The specific contact resistance of Ni (10 nm) / Au (30 nm) contacts deposited on the InGaN capping layers was determined by the transmission line method. Specific contact resistances of 1.2 × 10-2 Ω cm2 and 6 × 10-3 & cm2 were obtained for capping layer thicknesses of 20 nm and 2 nm, respectively.

Low-resistance electrical contacts to single crystal BSCCO whiskers

1995 ◽  
Vol 8 (9) ◽  
pp. 718-725 ◽  
Author(s):  
S Aukkaravittayapun ◽  
K A Benedict ◽  
I G Gorlova ◽  
P J King ◽  
Yu I Latyshev ◽  
...  
Keyword(s):  
Single Crystal ◽  
Electrical Contacts ◽  
Low Resistance

scholarly journals Low-Resistance, High-Yield Electrical Contacts to Atom Scale Si:P Devices Using Palladium Silicide

2019 ◽  
Vol 11 (3) ◽  
Author(s):  
Scott W. Schmucker ◽  
Pradeep N. Namboodiri ◽  
Ranjit Kashid ◽  
Xiqiao Wang ◽  
Binhui Hu ◽  
...  
Keyword(s):  
Electrical Contacts ◽  
High Yield ◽  
Low Resistance ◽  
Palladium Silicide

Development of low resistance electrical contacts for thermoelectric devices based on n-type PbTe and p-type TAGS-85 ((AgSbTe2)0.15(GeTe)0.85)

2008 ◽  
Vol 42 (1) ◽  
pp. 015502 ◽  
Author(s):  
Ajay Singh ◽  
S Bhattacharya ◽  
C Thinaharan ◽  
D K Aswal ◽  
S K Gupta ◽  
...  
Keyword(s):  
Electrical Contacts ◽  
Thermoelectric Devices ◽  
Low Resistance ◽  
P Type
Sign in / Sign up

Export Citation Format

Share Document