Precision, transistorized summing amplifier

1963 ◽  
Vol 6 (6) ◽  
pp. 500-505
Author(s):  
V. A. Bulgakov ◽  
A. S. Eremin ◽  
B. S. Rozov
Keyword(s):  
Summing Amplifier

An Ultra-Low-Power, 16 Bits CT Delta-Sigma Modulator Using 4-Bit Asynchronous SAR Quantizer for Medical Applications

2019 ◽  
Vol 29 (04) ◽  
pp. 2050056
Author(s):  
Sahel Javahernia ◽  
Esmaeil Najafi Aghdam ◽  
Pooya Torkzadeh
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Digital To Analog Converter ◽  
Ultra Low Power ◽  
Feed Forward ◽  
Delta Sigma Modulator ◽  
Delta Sigma ◽  
Summing Amplifier ◽  
Capacitor Structure ◽  
Asynchronous Sar

In this paper, a low-power second-order feed-forward capacitor-structure continuous-time [Formula: see text] modulator with a 4-bit asynchronous successive approximation register (SAR) quantizer is presented. Through the utilization capacitor structure in the proposed modulator, first, the summation node of the integrators’ outputs and the feed-forward signals is implemented within the second integrator to reduce power consumption by eliminating an active summing amplifier. Second, the proposed architecture can compensate for the quantizer delay without using any excess inner digital to analog converter (DAC). In this design, the modulator applies two different low-power operational amplifiers. These advantages cause the modulator to consume very low power and achieve a favorable figure of merit (FOM) value. In fact, in this paper, the combination of the previously reported methods and designs and doing required reforms has led to a new design with better performance, especially in power reduction. The designed modulator which is simulated using 0.18[Formula: see text][Formula: see text]m CMOS technology achieves 95.98[Formula: see text]dB peak signal-to-noise and distortion (SNDR) for 10[Formula: see text]KHz signal bandwidth and dissipates 44[Formula: see text][Formula: see text]w while its FOM is obtained about 43 fJ/conv.-step.

Summing Amplifier

1969 ◽  
Vol 40 (4) ◽  
pp. 598-599 ◽  
Author(s):  
Cassimer M. Kukla
Keyword(s):  
Summing Amplifier

scholarly journals Linearity Enhancement of VCO-Based Continuous-Time Delta-Sigma ADCs Using Digital Feedback Residue Quantization

Electronics ◽  
2021 ◽  
Vol 10 (22) ◽  
pp. 2773
Author(s):  
Moo-Yeol Choi ◽  
Bai-Sun Kong
Keyword(s):  
Continuous Time ◽  
Voltage Controlled Oscillator ◽  
Switching Noise ◽  
Signal To Noise ◽  
Analog To Digital ◽  
Delta Sigma ◽  
Summing Amplifier ◽  
Noise Injection ◽  
Voltage Swing ◽  
Δσ Adc

A linearity enhancement scheme for voltage-controlled oscillator (VCO)-based continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converters (ADCs) is proposed. Unlike conventional input feedforwarding techniques, the proposed feedforwarding scheme using digital feedback residue quantization (DFRQ) can avoid the analog summing amplifier, allow intrinsic anti-aliasing filtering (AAF) characteristic, and cause no switching noise injection into the input. A VCO-based CT ΔΣ ADC adapting the proposed DFRQ enables residue-only processing in the quantizer, avoiding the degradation of signal-to-noise and distortion ratio (SNDR) due to VCO nonlinearity. The use of DFRQ also reduces the voltage swing of integrators without the drawbacks caused by conventional input feedforwarding techniques. The performance evaluation results indicate that the proposed VCO-based CT ΔΣ ADC with DFRQ provides 30.3-dB SNDR improvement, reaching up to 83.5-dB in 2-MHz signal bandwidth.

scholarly journals RANCANG BANGUN MODUL ELECTRICAL POWER DEMAND UNTUK SIMULATOR INSTALASI PLTN

2017 ◽  
Vol 7 (2) ◽  
pp. 138
Author(s):  
Ikhsan Shobari ◽  
Dian Fitri Atmoko ◽  
Syahrudin Yusuf ◽  
Sutomo Budihardjo
Keyword(s):  
Electrical Power ◽  
Power Demand ◽  
Summing Amplifier ◽  
Lab View

RANCANG BANGUN MODUL ELECTRICAL POWER DEMAND UNTUK SIMULATOR INSTALASI PLTN. Telah dilakukan kegiatan rancang bangun modul electrical power demand yang berfungsi untuk mensimulasikan perubahan beban listrik. Modul electrical power demand merupakan bagian dari simulator instalasi PLTN. Bagian lainnya adalah simulator teras reaktor dan simulator turbin generator, yang setelah diintegrasikan akan menjadi simulator instalasi PLTN. Bagian utama electrical power demand simulator instalasi PLTN adalah modul beban, modul summing amplifier, modul data akuisisi NI 6212, modul kendali PLC T100MD series, dan modul perangkat tampilan informasi proses dan perangkat lunak kendali. Modul perangkat lunak tampilan informasi proses dibangun dengan program Lab View 2009 Evaluation Version dan untuk modul kendali digunakan perangkat lunak Trilogi Versi 6. 13. Dari hasil pengujian electrical power demand yang diintegrasikan, dapat difungsikan sebagai sarana pembelajaran pengoperasian sebuah instalasi PLTN dengan fluktuasi dan dinamika perubahan beban listrik.

scholarly journals Multi-State MRAM Cells For Hardware Neuromorphic Computing

2021 ◽  
Author(s):  
Piotr Rzeszut ◽  
Jakub Chęciński ◽  
Ireneusz Brzozowski ◽  
Sławomir Ziętek ◽  
Witold Skowroński ◽  
...  
Keyword(s):  
Memory Cell ◽  
Information Storage ◽  
Sigmoid Function ◽  
Digital Information ◽  
Function Generator ◽  
Random Number Generators ◽  
Computing Device ◽  
Summing Amplifier ◽  
Potential Applications ◽  
Storage Technologies

Abstract Magnetic tunnel junctions (MTJ) have been successfully applied in various sensing application and digital information storage technologies. Currently, a number of new potential applications of MTJs are being actively studied, including high-frequency electronics, energy harvesting or random number generators. Recently, MTJs have been also proposed in designs of new platforms for unconventional or bio-inspired computing. In the present work, it is shown that serially connected MTJs forming a multi-state memory cell can be used in a hardware implementation of a neural computing device. The main purpose of the multi-cell is the formation of quantized weights in the network, which can be programmed using the proposed electronic circuit. Multi-cells are connected to a CMOS-based summing amplifier and a sigmoid function generator, forming an artificial neuron. The operation of the designed network is tested using a recognition of hand-written digits in 20 × 20 pixels matrix and shows detection ratio comparable to the software algorithm, using weights stored in a multi-cell consisting of four MTJs or more.

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