A VLSI design methodology for distributed arithmetic

Wayne P. Burleson; Louis L. Scharf

doi:10.1007/bf00925468

A VLSI design methodology for distributed arithmetic

The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology ◽

10.1007/bf00925468 ◽

1991 ◽

Vol 2 (4) ◽

pp. 235-252 ◽

Cited By ~ 24

Author(s):

Wayne P. Burleson ◽

Louis L. Scharf

Keyword(s):

Design Methodology ◽

Vlsi Design ◽

Distributed Arithmetic ◽

Vlsi Design Methodology

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A look-up table VLSI design methodology for RNS structures used in DSP applications

IEEE Transactions on Circuits and Systems ◽

10.1109/tcs.1987.1086188 ◽

1987 ◽

Vol 34 (6) ◽

pp. 604-616 ◽

Cited By ~ 34

Author(s):

M. Bayoumi ◽

G. Jullien ◽

W. Miller

Keyword(s):

Design Methodology ◽

Vlsi Design ◽

Look Up Table ◽

Vlsi Design Methodology ◽

Dsp Applications

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VLSI Design Methodology for Edge-Preserving Image Reconstruction

Real-Time Imaging ◽

10.1006/rtim.2000.0215 ◽

2001 ◽

Vol 7 (1) ◽

pp. 109-126 ◽

Cited By ~ 7

Author(s):

Étienne Mémin ◽

Tanguy Risset

Keyword(s):

Image Reconstruction ◽

Design Methodology ◽

Vlsi Design ◽

Edge Preserving ◽

Vlsi Design Methodology

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NP-Separate: A New VLSI Design Methodology for Area, Power, and Performance Optimization

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2020.2966551 ◽

2020 ◽

pp. 1-1

Author(s):

Monzurul Islam Dewan ◽

Dae Hyun Kim

Keyword(s):

Performance Optimization ◽

Design Methodology ◽

Vlsi Design ◽

Vlsi Design Methodology ◽

And Performance

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VLSI design methodology for ASIC development

Microelectronics Journal ◽

10.1016/s0026-2692(87)80388-9 ◽

1987 ◽

Vol 18 (4) ◽

pp. 44

Keyword(s):

Design Methodology ◽

Vlsi Design ◽

Vlsi Design Methodology

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A low-power VLSI design methodology for high bit-rate data communications over UTP channel

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187) ◽

10.1109/iscas.1998.705314 ◽

2002 ◽

Cited By ~ 1

Author(s):

M. Goez ◽

N.R. Shanbhag

Keyword(s):

Low Power ◽

Design Methodology ◽

Vlsi Design ◽

Data Communications ◽

Rate Data ◽

Bit Rate ◽

High Bit Rate ◽

Vlsi Design Methodology ◽

Low Power Vlsi Design

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VLSI design methodology workshop

19th Design Automation Conference ◽

10.1145/800263.809287 ◽

1982 ◽

Author(s):

J. D. Nash

Keyword(s):

Design Methodology ◽

Vlsi Design ◽

Vlsi Design Methodology

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Electronic Sleep Stage Classifiers: A Survey and VLSI Design Methodology

IEEE Transactions on Biomedical Circuits and Systems ◽

10.1109/tbcas.2016.2540438 ◽

2017 ◽

Vol 11 (1) ◽

pp. 177-188 ◽

Cited By ~ 17

Author(s):

Hossein Kassiri ◽

Aditi Chemparathy ◽

M. Tariqus Salam ◽

Richard Boyce ◽

Antoine Adamantidis ◽

...

Keyword(s):

Design Methodology ◽

Sleep Stage ◽

Vlsi Design ◽

Vlsi Design Methodology

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VLSI Design Methodology - the Problem of the 80's for Microprocessor Design

10.1109/dac.1979.1600166 ◽

1979 ◽

Cited By ~ 24

Author(s):

B. Lattin

Keyword(s):

Design Methodology ◽

Vlsi Design ◽

Microprocessor Design ◽

Vlsi Design Methodology

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A full custom VLSI design methodology using Mentor Graphics design software in an educational environs

Sixth Annual IEEE International ASIC Conference and Exhibit ◽

10.1109/asic.1993.410728 ◽

2002 ◽

Author(s):

T.K. Schneider ◽

A.J. Schwab ◽

J.H. Aylor

Keyword(s):

Design Methodology ◽

Vlsi Design ◽

Vlsi Design Methodology ◽

Design Software ◽

Graphics Design

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A VLSI design methodology for RNS full adder-based inner product architectures

IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing ◽

10.1109/82.566648 ◽

1997 ◽

Vol 44 (4) ◽

pp. 315-318 ◽

Cited By ~ 22

Author(s):

D.J. Soudris ◽

V. Paliouras ◽

T. Stouraitis ◽

C.E. Goutis

Keyword(s):

Design Methodology ◽

Vlsi Design ◽

Full Adder ◽

Inner Product ◽

Vlsi Design Methodology

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