A high-speed transmission method for wireless personal communications

1996 ◽  
Vol 3 (3) ◽  
pp. 299-317 ◽  
Author(s):  
K. Ben Letaief ◽  
J. C. -I. Chuang ◽  
R. D. Murch
2017 ◽  
Vol 95 (3) ◽  
pp. 3493-3493
Author(s):  
Siddig Gomha ◽  
Abdel-Aziz T. Shalaby ◽  
EL-Sayed M. El-Rabaie ◽  
Ahmed S. Elkorany ◽  
Asmaa Rady ◽  
...  

1996 ◽  
Vol 14 (4) ◽  
pp. 609-622 ◽  
Author(s):  
F. Borgonovo ◽  
M. Zorzi ◽  
L. Fratta ◽  
V. Trecordi ◽  
G. Bianchi

2012 ◽  
Vol 229-231 ◽  
pp. 1543-1546
Author(s):  
Xiao Bo Zhou ◽  
Min Xia ◽  
Hai Long Cheng

To improve data transmission performance of the data acquisition card, a design of high-speed data transmission system is proposed in the thesis. Using FPGA of programmable logic devices, adopting Verilog HDL of hardware description language, the design of modularization and DMA transmission method is implemented in FPGA. Eventually the design implements the data transmission with high-speed through PCI Express interface. Through simulation and verification based on hardware system, this design is proved to be feasible and can satisfy the performance requirements of data transmission in the high-speed data acquisition card applied in high-speed railway communication. The design also has some value of application and reference for a universal data acquisition card.


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