Transparent random access memory testing for pattern sensitive faults

1996 ◽  
Vol 9 (3) ◽  
pp. 251-266 ◽  
Author(s):  
M. G. Karpovsky ◽  
V. N. Yarmolik
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Memory Testing ◽  
Access Memory ◽  
Pattern Sensitive Faults

Analysis of FSRAM Single Bit Failures Due to Unique Dislocations

1998 ◽  
Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  
Keyword(s):  
Electron Microscopy ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Temperature Sensitive ◽  
Wafer Level ◽  
Top Down ◽  
Access Memory ◽  
Transmission Electron ◽  
Contact Processing

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.

Deprocessing Methodologies for Detection of IBC and Cell-to-Cell Shorts in Submicron DRAM

2012 ◽  
Author(s):  
Ramachandra Chitakudige ◽  
Sarat Kumar Dash ◽  
A.M. Khan
Keyword(s):  
High Selectivity ◽  
Electron Cyclotron Resonance ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Plasma System ◽  
Poly Silicon ◽  
Hazardous Gases ◽  
Wet Etch ◽  
Resonance Plasma

Abstract Detection of both Insufficient Buried Contact (IBC) and cell-to-cell short defects is quite a challenging task for failure analysis in submicron Dynamic Random Access Memory (DRAM) devices. A combination of a well-controlled wet etch and high selectivity poly silicon etch is a key requirement in the deprocessing of DRAM for detection of these types of failures. High selectivity poly silicon etch methods have been reported using complicated system such as ECR (Electron Cyclotron Resonance) Plasma system. The fact that these systems use hazardous gases like Cl2, HBr, and SF6 motivates the search for safer alternative deprocessing chemistries. The present work describes high selectivity poly silicon etch using simple Reactive Ion Etch (RIE) plasma system using less hazardous gases such as CF4, O2 etc. A combination of controlled wet etch and high selectivity poly silicon etch have been used to detect both IBC and cell-to-cell shorts in submicron DRAMs.

Challenges and Benefits of Product-Like SRAM in Technology Development

2011 ◽  
Author(s):  
Felix Beaudoin ◽  
Stephen Lucarini ◽  
Fred Towler ◽  
Stephen Wu ◽  
Zhigang Song ◽  
...  
Keyword(s):  
Technology Development ◽  
Random Access ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Development Phase ◽  
High Complexity ◽  
Access Memory ◽  
Integration Schemes ◽  
Front End

Abstract For SRAMs with high logic complexity, hard defects, design debug, and soft defects have to be tackled all at once early on in the technology development while innovative integration schemes in front-end of the line are being validated. This paper presents a case study of a high-complexity static random access memory (SRAM) used during a 32nm technology development phase. The case study addresses several novel and unrelated fail mechanisms on a product-like SRAM. Corrective actions were put in place for several process levels in the back-end of the line, the middle of the line, and the front-end of the line. These process changes were successfully verified by demonstrating a significant reduction of the Vmax and Vmin nest array block fallout, thus allowing the broader development team to continue improving random defectivity.

Effect of Conductive Filament Temperature on ZrO2 based Resistive Random Access Memory Devices

2020 ◽  
Vol 12 (2) ◽  
pp. 02008-1-02008-4
Author(s):  
Pramod J. Patil ◽  
◽  
Namita A. Ahir ◽  
Suhas Yadav ◽  
Chetan C. Revadekar ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Memory Devices ◽  
Access Memory ◽  
Conductive Filament ◽  
Filament Temperature

scholarly journals Improved Device Distribution in High-Performance SiNx Resistive Random Access Memory via Arsenic Ion Implantation

Nanomaterials ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 1401
Author(s):  
Te Jui Yen ◽  
Albert Chin ◽  
Vladimir Gritsenko
Keyword(s):  
High Performance ◽  
Conduction Mechanism ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Switching Behavior ◽  
Access Memory ◽  
Current Voltage ◽  
Current Voltage Characteristics ◽  
Limited Conduction

Large device variation is a fundamental challenge for resistive random access memory (RRAM) array circuit. Improved device-to-device distributions of set and reset voltages in a SiNx RRAM device is realized via arsenic ion (As+) implantation. Besides, the As+-implanted SiNx RRAM device exhibits much tighter cycle-to-cycle distribution than the nonimplanted device. The As+-implanted SiNx device further exhibits excellent performance, which shows high stability and a large 1.73 × 103 resistance window at 85 °C retention for 104 s, and a large 103 resistance window after 105 cycles of the pulsed endurance test. The current–voltage characteristics of high- and low-resistance states were both analyzed as space-charge-limited conduction mechanism. From the simulated defect distribution in the SiNx layer, a microscopic model was established, and the formation and rupture of defect-conductive paths were proposed for the resistance switching behavior. Therefore, the reason for such high device performance can be attributed to the sufficient defects created by As+ implantation that leads to low forming and operation power.

Sign in / Sign up

Export Citation Format

Share Document